Search results for "Jürgen Teich"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jürgen Teich	Hardware/Software Codesign: The Past, the Present, and Predicting the Future.	Proceedings of the IEEE	2012	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich	Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.	ARCS	2012	DBLP DOI BibTeX RDF
1	Yang Xu, Rafael Rosales, Bo Wang, Martin Streubühr, Ralph Hasholzner, Christian Haubelt, Jürgen Teich	A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology.	ARCS	2012	DBLP DOI BibTeX RDF
1	Dirk Koch, Jim Torresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele	Partial Reconfiguration on FPGAs in Practice - Tools and Applications.	ARCS Workshops	2012	DBLP BibTeX RDF
1	Sascha Roloff, Frank Hannig, Jürgen Teich	Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich	Designing FlexRay-based automotive architectures: A holistic OEM approach.	DATE	2012	DBLP BibTeX RDF
1	Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich	Variation-aware leakage power model extraction for system-level hierarchical power analysis.	DATE	2012	DBLP BibTeX RDF
1	Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt	FlexRay Static Segment Scheduling.	Advances in Real-Time Systems	2012	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich	Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays.	Embedded Systems Letters	2011	DBLP DOI BibTeX RDF
1	Joachim Keinert, Jürgen Teich	Design of Image Processing Embedded Systems Using Multidimensional Data Flow		2011	DOI RDF
1	Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, Gregor Snelting	Invasive Computing: An Overview.	Multiprocessor System-on-Chip	2011	DBLP DOI BibTeX RDF
1	Tobias Ziermann, Stefan Wildermann, Jürgen Teich	OrganicBus: Organic Self-organising Bus-Based Communication Systems.	Organic Computing	2011	DBLP DOI BibTeX RDF
1	Rainer Kiesel, Martin Streubühr, Christian Haubelt, Otto Löhlein, Jürgen Teich	Calibration and validation of software performance models for pedestrian detection systems.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Martin Lukasiewycz, Michael Glaß, Felix Reimann, Jürgen Teich	Opt4J: a modular framework for meta-heuristic optimization.	GECCO	2011	DBLP DOI BibTeX RDF
1	Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich	Stress-Aware Module Placement on Reconfigurable Devices.	FPL	2011	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Jürgen Teich, Daniel Ziener	Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs.	FPL	2011	DBLP DOI BibTeX RDF
1	Philipp Kutzer, Jens Gladigau, Christian Haubelt, Jürgen Teich	Automatic generation of system-level virtual prototypes from streaming application models.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration.	ARCS	2011	DBLP DOI BibTeX RDF
1	Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich	Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa.	ARCS	2011	DBLP DOI BibTeX RDF
1	Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich	Dynamic decentralized mapping of tree-structured applications on NoC architectures.	NOCS	2011	DBLP BibTeX RDF
1	Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau	Resource-aware programming and simulation of MPSoC architectures through extension of X10.	SCOPES	2011	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic	Operational mode exploration for reconfigurable systems with multiple applications.	FPT	2011	DBLP DOI BibTeX RDF
1	Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich	Runtime stress-aware replica placement on reconfigurable devices under safety constraints.	FPT	2011	DBLP DOI BibTeX RDF
1	Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich	An FPGA implementation of a threat-based strategy for Connect6.	FPT	2011	DBLP DOI BibTeX RDF
1	Vahid Lari, Frank Hannig, Jürgen Teich	Distributed Resource Reservation in Massively Parallel Processor Arrays.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Josef Angermeier, Eugen Sibirko, Rolf Wanka, Jürgen Teich	Bitonic Sorting on Dynamically Reconfigurable Architectures.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich	Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor.	MARC Symposium	2011	DBLP BibTeX RDF
1	Felix Reimann, Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich	Symbolic system synthesis in the presence of stringent real-time constraints.	DAC	2011	DBLP DOI BibTeX RDF
1	Andreas Kern, Helge Zinner, Thilo Streichert, Josef Nöbauer, Jürgen Teich	Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks.	DAC	2011	DBLP DOI BibTeX RDF
1	Tobias Ziermann, Zoran Salcic, Jürgen Teich	Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems.	ATC	2011	DBLP DOI BibTeX RDF
1	Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich	Decentralized dynamic resource management support for massively parallel processor arrays.	ASAP	2011	DBLP DOI BibTeX RDF
1	Martin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich	ESL power and performance estimation for heterogeneous MPSOCS using SystemC.	FDL	2011	DBLP BibTeX RDF
1	Andreas Kern, Hongyan Zhang, Thilo Streichert, Jürgen Teich	Testing switched Ethernet networks in automotive embedded systems.	SIES	2011	DBLP DOI BibTeX RDF
1	Tobias Ziermann, Jürgen Teich, Zoran Salcic	DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems.	DATE	2011	DBLP BibTeX RDF
1	Andreas Kern, Thilo Streichert, Jürgen Teich	An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP).	DATE	2011	DBLP BibTeX RDF
1	Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich	A rule-based static dataflow clustering algorithm for efficient embedded software synthesis.	DATE	2011	DBLP BibTeX RDF
1	Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade	Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich	Symbolic design space exploration for multi-mode reconfigurable systems.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang	Mapping of applications to MPSoCs.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich	Design and architectures for dependable embedded systems.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Joachim Falk, Christian Zebelein, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya	Analysis of SystemC actor networks for efficient synthesis.	ACM Trans. Embedded Comput. Syst.	2010	DBLP DOI BibTeX RDF
1	Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich	No-Break Dynamic Defragmentation of Reconfigurable	CoRR	2010	DBLP BibTeX RDF
1	Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich	Maintaining Virtual Areas on FPGAs using Strip Packing with Delays	CoRR	2010	DBLP BibTeX RDF
1	Udo Kebschull, Marco Platzner, Jürgen Teich	Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial].	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich	Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich	ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen	ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Marco Platzner, Jürgen Teich, Norbert Wehn (eds.)	Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications.		2010	DBLP DOI BibTeX RDF
1	Christian Haubelt, Jürgen Teich	Digitale Hardware/Software-Systeme: Spezifikation und Verifikation		2010	DOI RDF
1	Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich	A system-level synthesis approach from formal application models to generic bus-based MPSoCs.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch	A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs.	FPL	2010	DBLP DOI BibTeX RDF
1	Richard Membarth, Anton Lokhmotov, Jürgen Teich	Generating GPU Code from a High-Level Representation for Image Processing Kernels.	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
1	Samarjit Chakraborty, S. Ramesh, Jürgen Teich	Model-based analysis, synthesis and testing of automotive hardware/software architectures.	EMSOFT	2010	DBLP DOI BibTeX RDF
1	Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger	A deeply pipelined and parallel architecture for denoising medical images.	FPT	2010	DBLP DOI BibTeX RDF
1	Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich	Virtual area management: Multitasking on dynamically partially reconfigurable devices.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Tobias Ziermann, Jürgen Teich	Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich	Towards scalable system-level reliability analysis.	DAC	2010	DBLP DOI BibTeX RDF	SAT-assisted simulation, early quantification, reliability analysis
1	Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hübner, Jürgen Teich	Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems.	ICCCN	2010	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic	Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras.	ATC	2010	DBLP DOI BibTeX RDF
1	François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski (eds.)	21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010	ASAP	2010	DBLP BibTeX RDF
1	Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich	Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems.	FCCM	2010	DBLP DOI BibTeX RDF
1	Daniel Ziener, Florian Baueregger, Jürgen Teich	Using the Power Side Channel of FPGAs for Communication.	FCCM	2010	DBLP DOI BibTeX RDF
1	Daniel Ziener, Florian Baueregger, Jürgen Teich	Multiplexing Methods for Power Watermarking.	HOST	2010	DBLP DOI BibTeX RDF
1	Martin Lukasiewycz, Michael Glaß, Jürgen Teich	Robust design of embedded systems.	DATE	2010	DBLP BibTeX RDF
1	Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch	Efficient High-Level modeling in the networking domain.	DATE	2010	DBLP BibTeX RDF
1	Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich	A rapid prototyping system for error-resilient multi-processor systems-on-chip.	DATE	2010	DBLP BibTeX RDF
1	Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich	Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich	Symbolic system level reliability analysis.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Felix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich	Improving platform-based system synthesis by satisfiability modulo theories solving.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier	A holistic approach for tightly coupled reconfigurable parallel processors.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Nikil Dutt, Jürgen Teich	CODES+ISSS 2007 guest editors' introduction.	Design Autom. for Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith	SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	System design, hardware/software codesign
1	Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor Stefanov, Daniel D. Gajski, Jürgen Teich	Electronic System-Level Synthesis Methodologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Dirk Koch, Christian Beckhoff, Jürgen Teich	Hardware Decompression Techniques for FPGA-Based Embedded Systems.	TRETS	2009	DBLP DOI BibTeX RDF	reconfigurable computing, configuration, Bitstream
1	Stefan Wildermann, Tobias Ziermann, Jürgen Teich	Self-organizing Bandwidth Sharing in Priority-Based Medium Access.	SASO	2009	DBLP DOI BibTeX RDF
1	Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich	Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich	Self-organizing multi-cue fusion for FPGA-based embedded imaging.	FPL	2009	DBLP DOI BibTeX RDF
1	Josef Angermeier, Abdulazim Amouri, Jürgen Teich	General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems.	FPL	2009	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Jürgen Teich	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.	ARCS	2009	DBLP DOI BibTeX RDF
1	Frank Hannig, Hritam Dutta, Jürgen Teich	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.	ARCS	2009	DBLP DOI BibTeX RDF
1	Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty	Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	design space exploration, timing analysis, automotive
1	Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich	Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.	ASAP	2009	DBLP DOI BibTeX RDF
1	Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich	Impact of Loop Tiling on the Controller Logic of Acceleration Engines.	ASAP	2009	DBLP DOI BibTeX RDF
1	Joon Edward Sim, Weng-Fai Wong, Jürgen Teich	Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators.	FCCM	2009	DBLP DOI BibTeX RDF	Reconfiguration Scheduling, FPGA, Reconfigurable Computing, Partial Reconfiguration
1	Dirk Koch, Christian Beckhoff, Jürgen Teich	Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems.	FCCM	2009	DBLP DOI BibTeX RDF
1	Martin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich	Efficient approximately-timed performance modeling for architectural exploration of MPSoCs.	FDL	2009	DBLP BibTeX RDF
1	Dirk Koch, Christian Beckhoff, Jürgen Teich	A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, reconfiguration, communication architecture
1	Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich	Combined system synthesis and communication architecture exploration for MPSoCs.	DATE	2009	DBLP BibTeX RDF
1	Tobias Ziermann, Stefan Wildermann, Jürgen Teich	CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates.	DATE	2009	DBLP BibTeX RDF
1	Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich	Incorporating graceful degradation into embedded system design.	DATE	2009	DBLP BibTeX RDF
1	Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich	Model-based synthesis and optimization of static multi-rate image processing algorithms.	DATE	2009	DBLP BibTeX RDF
1	Vahid Lari, Frank Hannig, Jürgen Teich	System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Martin Lukasiewycz, Michael Glaß, Jürgen Teich	Exploiting data-redundancy in reliability-aware networked embedded system design.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	reliability, design space exploration, networked embedded systems
1	Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt	FlexRay schedule optimization of the static segment.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, optimization, FlexRay
1	Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich	Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Daniel Ziener, Jürgen Teich	Power Signature Watermarking of IP Cores for FPGAs.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	IPP, FPGA, watermarking, signature, power analysis, IP cores
1	Jürgen Teich	Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen).	it - Information Technology	2008	DBLP DOI BibTeX RDF

Publications of "Jürgen Teich" ( http://dblp.L3S.de/Authors/Jürgen_Teich )