Search results for "J. Electronic Testing"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Thelma Elita Colanzi, Wesley Klewerton Guez Assunção, Daniela de Freitas Guilhermino Trindade, Carlos Alberto Zorzo, Silvia Regina Vergilio	Evaluating Different Strategies for Testing Software Product Lines.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Xifeng Li, Yongle Xie	Analog Circuits Fault Detection Using Cross-Entropy Approach.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Kanad Chakraborty, James E. Kelly, Brian P. Evans	Novel Self-Timed, Pipelined Clock Scan Architecture.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Olivier Héron, Clement Bertolini, Chiara Sandionigi, Nicolas Ventroux, François Marc	On the Simulation of HCI-Induced Variations of IC Timings at High Level.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu	Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Edgar Leonardo Romero, Marius Strum, Wang Jiang Chau	Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Vishwani D. Agrawal	Eliminating the Timing Penalty of Scan.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	S. Bergaoui, A. Wecxsteen, Régis Leveugle	Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede	Secure JTAG Implementation Using Schnorr Protocol.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Said Hamdioui, Hans A. R. Manhaeve	Guest Editorial - Special Issue on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN).	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Ashok Kavithamani, Venugopal Manikandan, Nanjundappan Devarajan	Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1		2012 JETTA Reviewers.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Ismail Akturk, Ozcan Ozturk	Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor	Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone	Testing of Synchronizers in Asynchronous FIFO.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1		Test Technology Newsletter.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Viktor Mashkov, Jiri Barilla, Pavel Simr	Applying Petri Nets to Modeling of Many-Core Processor Self-Testing when Tests are Performed Randomly.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1		Test Technology Newsletter.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Natalja Kehl, Wolfgang Rosenstiel	Circuit Level Concurrent Error Detection in FSMs.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Wassim Mansour, Raoul Velazco	SEU Fault-Injection in VHDL-Based Processors: A Case Study.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1		New Editors, 2013.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Zhichao Zhang, Yi Ren, Li Chen, Nelson J. Gaspard, Arthur F. Witulski, W. Timothy Holman, Bharat L. Bhuva, Shi-Jie Wen, Ramaswami Sammynaiken	A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Han Han, Houjun Wang, Shulin Tian, Na Zhang	A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Matteo Carminati, Antonio Miele	Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems.	J. Electronic Testing	2013	DBLP DOI BibTeX RDF
1	Claude Thibeault, Yassine Hariri, C. Hobeika	Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy, Henrik Hovsepyan, Ara Markosian, Ehrenfried Zschech, Rene Huebner	Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui	Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Michal Tadeusiewicz, Stanislaw Halgas	Multiple Soft Fault Diagnosis of Nonlinear Circuits Using the Continuation Method.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen	Optimization Methods for Post-Bond Testing of 3D Stacked ICs.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Suraj Sindia, Vishwani D. Agrawal, Virendra Singh	Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Samed Maltabas, Kemal Kulovic, Martin Margala	Novel Practical Built-in Current Sensors.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Erik Jan Marinissen, Chun-Chuan Chi, Mario H. Konijnenburg, Jouke Verbree	A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Mozar Naing, Dallas Webster, Nolan Blue, Rick Hudgens, Zahir Parkar, Sumeer Bhatara, Pankaj Gupta, Donald Y. C. Lie	Maximizing Parallel Testing in an FM Receiver.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1		Test Technology Newsletter.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Kemal Kulovic, Martin Margala	Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi	Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1		Test Technology Newsletter.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Xiaomei Chen, Xiaofeng Meng, Guohua Wang	A Modified Simulation-Based Multi-Signal Modeling for Electronic System.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Sukeshwar Kannan, Bruce C. Kim, Byoungchul Ahn	Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud	ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1		Test Technology Newsletter.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Marta Portela-Garcia, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, N. Marroni, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas	Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera	NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Erik Jan Marinissen, Yervant Zorian	Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Jingbo Duan, Bharath K. Vasan, Chen Zhao, Degang Chen, Randall L. Geiger	On Chip Signal Generators for Low Overhead ADC BIST.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Badar-ud-din Ahmed, Youren Wang, Rizwan Ullah, Najam-ud-din Ahmed	A Novel TOPSIS-Based Test Vector Compaction Technique for Analog Fault Detection.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira	Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi	CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Elie H. Sarraf, Ankit Kansal, Mrigank Sharma, Edmond Cretu	FPGA-based Novel Adaptive Scheme Using PN Sequences for Self-Calibration and Self-Testing of MEMS-based Inertial Sensors.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti	Cohesive Coverage Management: Simulation Meets Formal Methods.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham	Built-in Self Test of RF Subsystems with Integrated Detectors.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	K. Castellani-Coulié, Hassen Aziza, Gilles Micolau, Jean Michel Portal	Optimization of SEU Simulations for SRAM Cells Reliability under Radiation.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Jari Hannu, Juha Häkkinen, Juha-Veikko Voutilainen, Heli Jantunen, Markku Moilanen	Current State of the Mixed-Signal Test Bus 1149.4.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Minshun Wu, Degang Chen, Jingbo Duan	An Accurate and Cost-Effective Jitter Measurement Technique Using a Single Test Frequency.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Viacheslav Izosimov, Giuseppe Di Guglielmo, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Masahiro Fujita	Time-Constraint-Aware Optimization of Assertions in Embedded Software.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Suraj Sindia, Vishwani D. Agrawal, Virendra Singh	Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen	Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Kazuyuki Wakabayashi, Keisuke Kato, Takafumi Yamada, Osamu Kobayashi, Haruo Kobayashi, Fumitaka Abe, Kiichi Niitsu	Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Michael Buttrick, Sandip Kundu	On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Shao-Feng Hung, Hao-Chiao Hong	Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Kyriakos Christou, Maria K. Michael	A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar	On the Reuse of TLM Mutation Analysis at RTL.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Bing Long, Shulin Tian, Houjun Wang	Feature Vector Selection Method Using Mahalanobis Distance for Diagnostics of Analog Circuits Based on LS-SVM.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich	Structural Test and Diagnosis for Graceful Degradation of NoC Switches.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Yang Zhao, Krishnendu Chakrabarty, Bhargab B. Bhattacharya	Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Ireneusz Mrozek, Vyacheslav N. Yarmolik	Iterative Antirandom Testing.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Ashok Kavithamani, Venugopal Manikandan, Nanjundappan Devarajan	Fault Detection of Analog Circuits Using Network Parameters.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Hsiu-Ming (Sherman) Chang, David C. Keezer	Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Mohammed Ashfaq Shukoor, Vishwani D. Agrawal	Diagnostic Test Set Minimization and Full-Response Fault Dictionary.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1		Test Technology Newsletter.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara	Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Alexandre Boyer, S. Ben Dhia, B. Li, C. Lemoine, Bertrand Vrignon	Prediction of Long-term Immunity of a Phase-Locked Loop.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Benjamin Backes, Colin McDonough, Larry Smith, Wei Wang 0003, Robert E. Geer	Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	R. M. Ayadi, S. Mahresi, M. Masmoudi	Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Tsung-Yen Tsai, Sadok Aouini, Gordon W. Roberts	High Speed On-Chip Signal Generation for Debug and Diagnosis.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky, Ariel Lutenberg, Edmundo Gatti, Fernando Hernandez	A Test Platform for Dependability Analysis of SoCs Exposed to EMI and Radiation.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Stefan R. Vock, Omar Escalona, Colin Turner, Frank J. Owens	Challenges for Semiconductor Test Engineering: A Review Paper.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Hui Luo, Youren Wang, Hua Lin, Yuanyuan Jiang	A New Optimal Test Node Selection Method for Analog Circuit.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Kanad Chakraborty, Vishwani D. Agrawal	Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Hyunjin Kim, Jacob A. Abraham	A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Editorial.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Wilson Javier Perez Holguin, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, J. Velasco Medina	Software-Based Testing for System Peripherals.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Sachin Dileep Dasnurkar, Jacob A. Abraham	Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Yi Lou, Zhuo Yan, Fan Zhang, Paul D. Franzon	Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	S. Ben Dhia, Alexandre Boyer, Bertrand Vrignon, Mikaël Deobarro	IC Immunity Modeling Process Validation Using On-Chip Measurements.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	J. M. Ruiz, Raúl Fernández-Garcia, I. Gil, M. Morata	Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Shreyas Sen, Aritra Banerjee, Vishwanath Natarajan, Shyam Kumar Devarakond, Hyun Woo Choi, Abhijit Chatterjee	BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Didac Gómez, Josep Altet, Diego Mateo	On the Use of Static Temperature Measurements as Process Variation Observable.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Bing Long, Shulin Tian, Houjun Wang	Diagnostics of Filtered Analog Circuits with Tolerance Based on LS-SVM Using Frequency Features.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF

Publications at "J. Electronic Testing"( http://dblp.L3S.de/Venues/J._Electronic_Testing )