Search results for "J. Low Power Electronics"

Hits ?▲	Authors	Title	Venue	Year	Link
1	J. Mazurier, O. Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, J.-P. Noel, Marc Belleville, Olivier Faynot, T. Poiroux	Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'agostino, Andre Juge, Edith Beigné, Stéphane Girard	Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Julien De Vos, Denis Flandre, David Bol	Pushing Adaptive Voltage Scaling Fully on Chip.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Subhash Chander, Pramod Agarwal, Indra Gupta	Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Ge Chen, Saeid Nooshabadi	Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Rohit Dhiman, Rajeevan Chandel	Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Nadine Azémard, Marc Belleville	Selected Articles from the VARI 2011 Workshop.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang	A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Kamali, Masoumeh Ebrahimi, S. Mohammadi, Ali Afzali-Kusha, Juha Plosila	Adaptive Input-Output Selection Based On-Chip Router Architecture.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Vyasa Sai, Ajay Ogirala, Marlin H. Mickle	Low-Power Data Driven Symbol Decoder for a UHF Passive RFID Tag.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Yang Xu, Hu He, Zhizhong Tang	Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Kaushik Bhattacharyya, Pradip Mandal	Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Muhammad Tariqus Salam, Fayçal Mounaïm, Dang Khoa Nguyen, Mohamad Sawan	Low-Power Circuit Techniques for Epileptic Seizures Detection and Subsequent Neurostimulation.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc	Impact of Power Consumption and Temperature on Processor Lifetime Reliability.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen	Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Gabriel A. Rincón-Mora, Andres A. Blanco, Justin P. Vogt	A 1.3-μW, 0.6-μm CMOS Current-Frequency Analog-Digital Converter for Implantable Blood-Glucose Monitors.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Biswajit Maity, Soumya Gangula, Pradip Mandal	Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty	Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli	Inter-Plane Communication Methods for 3-D ICs.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez	Digital Adaptive Calibration of Multi-Step Analog to Digital Converters.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Pierre-Antoine Haddad, Geoffroy Gosset, Denis Flandre	Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Jean Michel Portal, Marc Bocquet, Damien Deleruyelle, Christophe Muller	Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao	Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty	Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang	Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq	Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Yi Zhang, Rajdeep Bondade, Dongsheng Ma	On-Chip Single-Inductor Multiple-Output Power Converter Design with Adaptive Cross Regulation and Supply Variation Control for Power-Efficient VLSI Systems.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac	Trading Accuracy for Power in a Multiplier Architecture.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian	12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	András Timár, Márta Rencz	Studying the Influence of Chip Temperatures on Timing Integrity Using Improved Power Modeling.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Jeff Pool, Anselmo Lastra, Montek Singh	Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	René van Leuken	Selected Articles from the PATMOS 2010 Workshop.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev	Self-Timed SRAM for Energy Harvesting Systems.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, A. K. Saxena, S. Dasgupta	Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Rashmi Nanda, Dejan Markovic	Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital Systems.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Laurent Bousquet, Fabio Cenni, Emmanuel Simeu	Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	R. S. Oliveira, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira	On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José Monteiro	Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira	Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici	Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Benjamin S. Mericli, Ajay Ogirala, Peter J. Hawrylak, Marlin H. Mickle	A Passive Radio Frequency Amplifier for Radio Frequency Identification Tags.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh	On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Shireesh Verma	A Special Issue on Low Power Design and Verification Techniques.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Claas Cornelius, Frank Sill Torres, Dirk Timmermann	Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Svetozar S. Broussev, Nikolay T. Tchamov	Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Sohaib Majzoub	Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCs.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Yangbo Wu, Jianping Hu	Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Weixun Wang, Prabhat Mishra	Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Jitendra Kanungo, S. Dasgupta	An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Biswajit Patra, Nayan Chandak, Amlan Chakrabarti	An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski	A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii	A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Abhijit Sil, Magdy Bayoumi	A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Rashmi Mehrotra, Tom English, Michel P. Schellekens, Steve Hollands, Emanuel M. Popovici	Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	José F. da Rocha, Marcelino B. dos Santos, José M. Dores Costa	Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi	Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	He Tang, Hui Zhao, Siqiang Fan, Xin Wang, Lin Lin, Qiang Fang, Jian Liu, Albert Z. Wang	Design Matrix Analysis for Capacitive Interpolation Flash ADC.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid	An Automated Power Emulation Framework for Embedded Software - Detecting Power-Critical Code Regions and Optimizing Software-Induced Power Consumption Peaks.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Md. Ibrahim Faisal, Zahra Jeddi, Esmaeil Amini, Magdy Bayoumi	A Flexible Architecture for Finite Field Galois Fields(2m) Arithmetic Processor.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu	Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Aya Mabrouki, Thierry Taris, Yann Deval, Jean-Baptiste Begueret	An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Edoardo Regini, Daeseob Lim, Tajana Simunic Rosing	Resource Management in Heterogeneous Wireless Sensor Networks.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	David Guerrero, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo	Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Bhanu Kapoor, Shireesh Verma	Power Management Design and Verification.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Miao Hu, Hai Helen Li, Yiran Chen, Xiaobin Wang	Spintronic Memristor: Compact Model and Statistical Analysis.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	J. Kevin Hicks, Dhireesha Kudithipudi	Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien	A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang	Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Tapas Kumar Kundu, Kolin Paul	Analyzing and Improving Performance and Energy Efficiency of Android.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Bruno Jacinto, Carlos Moreira, Marcelino Santos	Digital Sliding Mode Control of DC-DC Buck Converters.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Kyungseok Kim, Vishwani D. Agrawal	Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Malal Bathily, Bruno Allard, Frederic Hasbani, Vincent Pinon	Low-Power, Battery-Operated, Large-Bandwidth Analog Integrated DC/DC Step-Down Converters.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Nitin Chandrachoodan, Shankar Balachandran	24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Satendra Kumar Maurya, Lawrence T. Clark	A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Sergio Gómez, Francesc Moll	Lithography Aware Regular Cell Design Based on a Predictive Technology Model.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan	Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Akhilesh Kumar, Mohab Anis	Power-Yield Enhancement for Field Programmable Gate Arrays Under Process Variations.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Judit Freijedo, Lucía Costas, Jorge Semião, Juan J. Rodríguez-Andina, María José Moure, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira	Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun, Lincoln Lai Kan Leung, Jianping Guo, Yuen Sum Ng, Chi Fat Chan, Weiwei Shi, Yang Hong, Marco Ho, Ki-Leung Mak, Yanqing Ai	RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara	An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson	On-Chip Process Variability Monitoring Flow.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Tooraj Nikoubin, Mahdieh Grailoo, Sayyed Hasan Mozafari	Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Low-Leakage and Compact Registers with Easy-Sleep Mode.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Nikolaos Andrikos, Luciano Lavagno, Fabio Campi, Davide Pandini	Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Sohan Purohit, Marco Lanuzza, Martin Margala	Design Space Exploration of Split-Path Data Driven Dynamic Full Adder.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Alex Bystrov	Selected Peer-Reviewed Articles from the LPonTR 2009 Workshop.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Ashutosh Nandi, Rajeevan Chandel	Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino	A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Milos Krstic, Tomasz Król, Xin Fan, Eckhard Grass	Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Binu P. John, Abhishek Agrawal, Bob Steigerwald, Eugene B. John	Impact of Operating System Behavior on Battery Life.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Ying Teng, Baris Taskin	Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Ilia Polian	Power Supply Noise: Causes, Effects, and Testing.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Ka-Ming Keung, Akhilesh Tyagi	State Space Reconfigurability: A Low Energy Implementation Architecture for Self Modifying Finite Automata.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo	Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	D. Ramakrishnan, Y. L. Wu, W. B. Jone	Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas	Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Test Sequences with Reduced and Increased Switching Activity.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF

Publications at "J. Low Power Electronics"( http://dblp.L3S.de/Venues/J._Low_Power_Electronics )