Search results for "J. Solid-State Circuits"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Kshitij Yadav, Ioannis Kymissis, Peter R. Kinget	A 4.4-$\mu$ W Wake-Up Receiver Using Ultrasound Data.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger	Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Amin Arbabian, Steven Callender, Shinwon Kang, Mustafa Rangwala, Ali M. Niknejad	A 94 GHz mm-Wave-to-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Shih-Yuan Kao, Shen-Iuan Liu	A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz	A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Omar A. Hafiz, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis	Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Philip M. Chopp, Anas A. Hamoui	A 1-V 13-mW Single-Path Frequency-Translating ΔΣ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Kamran Souri, Youngcheol Chae, Kofi A. A. Makinwa	A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of ±0.15°C (3σ) From -55°C to 125°C.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester	Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Meisam Honarvar Nazari, Azita Emami-Neyestanak	A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai	Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Vivek De, Hideyuki Kabuo	Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Liming Xiu, Win-Ting Lin, Tsung-Ta Lee	Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath	A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Inyoung Choi, Heesong Seo, Bumman Kim	Accurate dB-Linear Variable Gain Amplifier With Gain Error Compensation.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tae-Hyoung Kim, Jian-Ping Wang, Chris H. Kim	A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Wei Deng, Kenichi Okada, Akira Matsuzawa	Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta	A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yan Li, Zhipeng Li, Oguzhan Uyar, Yehuda Avniel, Alexandre Megretski, Vladimir Stojanovic	High-Throughput Signal Component Separator for Asymmetric Multi-Level Outphasing Power Amplifiers.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam	Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Gerry Taylor, Ian Galton	A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Joung Won Park, Behzad Razavi	A Harmonic-Rejecting CMOS LNA for Broadband Radios.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jun Won Jung, Behzad Razavi	A 25-Gb/s 5-mW CMOS CDR/Deserializer.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Andrea Mazzanti, Pietro Andreani	A Push-Pull Class-C CMOS VCO.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jun-Seok Kim, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim	A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jinuk Luke Shin, Robert T. Golla, Hongping Li, Sudesna Dash, Youngmoon Choi, Alan Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister	The Next Generation 64b SPARC Core in a T4 SoC Processor.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byung-Chul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi	A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Simone Gambini, Karl Skucha, Paul Peng Liu, Jungkyu Kim, Reut Krigel	A 10 kPixel CMOS Hall Sensor Array With Baseline Suppression and Parallel Readout for Immunoassays.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi	An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee	An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Bing-Nan Fang, Jieh-Tsorng Wu	A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat	SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	A 128$\, \times$ 128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Tsung-Te Liu, Jan M. Rabaey	A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Peter Ossieur, Nasir A. Quadir, Stefano Porto, Cleitus Antony, Wei Han, Marc Rensing, Peter O'Brien, Paul D. Townsend	A 10 Gb/s Linear Burst-Mode Receiver in 0.25 µm SiGe: C BiCMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Alan Chi Wai Wong, Mark Dawkins, Gabriele Devita, Nick Kasparidis, Andreas G. Katsiamis, Oliver King, Franco Lauria, Johannes Schiff, Alison Burdett	A 1 V 5 mA Multimode IEEE 802.15.6/Bluetooth Low-Energy WBAN Transceiver for Biotelemetry Applications.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Nicola Cottini, Massimo Gottardi, Nicola Massari, Roberto Passerone, Zeev Smilansky	A 33 $\mu$ W 64$\, \times\, $ 64 Pixel Vision Sensor Embedding Robust Dynamic Background Subtraction for Event Detection and Scene Interpretation.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai	A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Chih-Wei Yao, Alan N. Willson Jr.	A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho	A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yanqing Zhang, Fan Zhang, Yousef Shakhsheer, Jason Silver, Alicia Klinefelter, Manohar Nagaraju, James Boley, Jagdish Nayayan Pandey, Aatmesh Shrivastava, Eric J. Carlson, Austin Wood, Benton H. Calhoun, Brian P. Otis	A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Tae-Hwang Kong, Young-Jin Woo, Se-Won Wang, Yong-Joon Jeon, Sung-Wan Hong, Gyu-Hyeong Cho	Zero$^{\rm th}$-Order Control of Boost DC-DC Converter With Transient Enhancement Scheme.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara	Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	William Biederman, Daniel J. Yeager, Nathan Narevsky, Aaron C. Koralek, Jose M. Carmena, Elad Alon, Jan M. Rabaey	A Fully-Integrated, Miniaturized (0.125 mm2) 10.5 µW Wireless Neural Sensor.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho	An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez	An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun	Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Pin-Hao Feng, Shen-Iuan Liu	Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Dusan Stepanovic, Borivoje Nikolic	A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Noah Sturcken, Eugene J. O'Sullivan, Naigang Wang, Philipp Herget, Bucknell C. Webb, Lubomyr T. Romankiw, Michele Petracca, Ryan Davies, Robert E. Fontana, Gary M. Decad, Ioannis Kymissis, Angel V. Peterchev, Luca P. Carloni, William J. Gallagher, Kenneth L. Shepard	A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa	Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki	A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Un-Ku Moon	New Associate Editor.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David Blaauw, Dennis Sylvester	Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda	A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Arun Paidimarri, Phillip M. Nadeau, Patrick P. Mercier, Anantha P. Chandrakasan	A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Maurits Ortmanns, Timothy Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai	Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Satoru Kato, Manabu Kagami	A 100-m Range 10-Frame/s 340,x,96-Pixel Time-of-Flight Depth Sensor in 0.18-µm CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Matthew Fojtik, Daeyeon Kim, Gregory K. Chen, Yu-Shiang Lin, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, David Blaauw, Dennis Sylvester	A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Omid Rajaee, Un-Ku Moon	Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo	A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Seyed Danesh, Jed Hurwitz, Keith Findlater, David Renshaw, Robert K. Henderson	A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jerald Yoo, Long Yan, Dina El-Damak, Muhammad Bin Altaf, Ali H. Shoeb, Anantha P. Chandrakasan	An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono	An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee	A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi	Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yi-Chieh Huang, Shen-Iuan Liu	A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer	Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Ioannis Savidis, Selçuk Köse, Eby G. Friedman	Power Noise in TSV-Based 3-D Integrated Circuits.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Tamer A. Ali, Robert J. Drost, Ron Ho, Chih-Kong Ken Yang	A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Pedram Lajevardi, Vladimir P. Petkov, Boris Murmann	A ΔΣ Interface for MEMS Accelerometers Using Electrostatic Spring Constant Modulation for Cancellation of Bondwire Capacitance Drift.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Sven Lütkemeier, Thorsten Jungeblut, Hans Kristian Otnes Berge, Snorre Aunet, Mario Porrmann, Ulrich Rückert	A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jinho Noh, Dongjun Lee, Jun-Gi Jo, Changsik Yoo	A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar	A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin D. Parker, José A. Tierno, A. Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman	An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Un-Ku Moon	New Associate Editor.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Steven Hsu, Amit Agarwal, Mark Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy	A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Kazushige Kanda, Noboru Shibata, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Naoki Kobayashi 0004, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, Yasuhiko Honda, Yosuke Kato, Shingo Zaitsu, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita	A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi	A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With $< ±0.5-ppm Frequency Stability and $< 1-ps Integrated Jitter.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins	A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Po-Shuan Weng, Hao-Yen Tang, Po-Chih Ku, Liang-Hung Lu	50 mV-Input Batteryless Boost Converter for Thermal Energy Harvesting.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Shang-Fu Yeh, Chih-Cheng Hsieh, Ka-Yi Yeh	A 3 Megapixel 100 Fps 2.8 $\mu$m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Wendemagegnehu T. Beyene, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Inipodu Murugan, Kun-Yung Ken Chang, Xingchao Chuck Yuan	A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Jonathan K. Brown, David D. Wentzloff	A GSM-Based Clock-Harvesting Receiver With -87 dBm Sensitivity for Sensor Network Wake-Up.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Simeon Realov, Kenneth L. Shepard	On-Chip Combined C-V/I-V Characterization System in 45-nm CMOS Technology.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda, Hideki Mutoh, Ryuta Hirose, Hideki Tominaga, Kenji Takubo, Yasushi Kondo, Shigetoshi Sugawa	A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim	A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Deepak Bhatia, Lin Xue, Pengfei Li, Qiuzhong Wu, Rizwan Bashirullah	High-Voltage Tolerant Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr	A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort	A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yoonmyung Lee, Suyoung Bang, Inhee Lee, Yejoong Kim, Gyouho Kim, Mohammad Hassan Ghaed, Pat Pannuto, Prabal Dutta, Dennis Sylvester, David Blaauw	A Modular 1 mm3 Die-Stacked Sensing Platform With Low Power I2C Inter-Die Communication and Multi-Modal Energy Harvesting.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Yusuke Oike, Abbas El Gamal	CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF
1	Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka	A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yahya M. Tousi, Omeed Momeni, Ehsan Afshari	A Novel CMOS High-Power Terahertz VCO Based on Coupled Oscillators: Theory and Implementation.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Charalambos M. Andreou, Savvas Koudounas, Julius Georgiou	A Novel Wide-Temperature-Range, 3.9 ppm/°C CMOS Bandgap Reference Circuit.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott	Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee	A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Heesong Seo, Inyoung Choi, Changjoon Park, Jehyung Yoon, Bumman Kim	A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Guansheng Li, Li Liu, Yiwu Tang, Ehsan Afshari	A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Ha Trong Than, George W. Sun, Geovanni S. Cuellar, Jiyang Zeng, Nate T. Schultz, Michael E. Moya, Younkyu Chung, Blythe C. Deckman, Michael P. DeLisio	Design and Performance of a 600-WC-Band Amplifier Using Spatially Combined GaAs FETs for Satellite Communications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF

Publications at "J. Solid-State Circuits"( http://dblp.L3S.de/Venues/J._Solid-State_Circuits )