Search results for "J. Solid-State Circuits"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Charalambos M. Andreou, Savvas Koudounas, Julius Georgiou	A Novel Wide-Temperature-Range, 3.9 ppm/°C CMOS Bandgap Reference Circuit.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott	Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee	A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Heesong Seo, Inyoung Choi, Changjoon Park, Jehyung Yoon, Bumman Kim	A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim	A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Rikky Muller, Simone Gambini, Jan M. Rabaey	A 0.013 mm2, 5 µW , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Hua Gao, Ross M. Walker, Paul Nuyujukian, Kofi A. A. Makinwa, Krishna V. Shenoy, Boris Murmann, Teresa H. Meng	HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 µm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Alexander Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Solomon Assefa, Fuad E. Doany, Min Yang, Joris Van Campenhout, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov	Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Emilia Noorsal, Kriangkrai Sooksood, Hongcheng Xu, Ralf Hornig, Joachim Becker, Maurits Ortmanns	A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yu-Chi Su, Keng-Yen Huang, Tse-Wei Chen, Yi-Min Tsai, Shao-Yi Chien, Liang-Gee Chen	A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw	A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Jihwan Kim, Woonyun Kim, Hamhee Jeon, Yan-Yu Huang, Youngchang Yoon, Hyungwook Kim, Chang-Ho Lee, Kevin T. Kornegay	A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun	A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yu-Te Liao, Huanfen Yao, Andrew Lingley, Babak A. Parviz, Brian P. Otis	A 3-µW CMOS Glucose Sensor for Wireless Contact-Lens Tear Glucose Monitoring.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Joohwa Kim, James F. Buckwalter	A Switchless, Q-Band Bidirectional Transceiver in 0.12-µm SiGe BiCMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan	A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Brandon Rumberg, David W. Graham	A Low-Power Magnitude Detector for Analysis of Transient-Rich Signals.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Mau-Chung Frank Chang	An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman	An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester	A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Chun-Ying Chen, Jiangfeng Wu, Juo-Jung Hung, Tianwei Li, Wenbo Liu, Wei-Ta Shih	A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm2 and 500 mW in 40 nm Digital CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh	Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko	A 28 nm 0.6 V Low Power DSP for Mobile Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Subhanshu Gupta, Daibashish Gangopadhyay, Hasnain Lakdawala, Jacques C. Rudell, David J. Allstot	A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass $\Sigma \Delta$ ADC in 0.13 $\mu$m CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee	A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito	A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Daniel Fernández, Luís Martínez-Alvarado, Jordi Madrenas	A Translinear, Log-Domain FPAA on Standard CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Zhenglin Yang, Libin Yao, Yong Lian	A 0.5-V 35-µW 85-dB DR Double-Sampled ΔΣ Modulator for Audio Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yingchieh Ho, Chauchin Su	A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Georg Boeck	Overview for the Special Section on the 2011 Radio Frequency Integrated Circuits (RFIC) Symposium.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim	A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang, Li-Rong Zheng	The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Danilo Manstretta	A Broadband Low-Power Low-Noise Active Balun With Second-Order Distortion Cancellation.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Denis Foley, Pankaj Bansal, Don Cherepacha, Robert Wasmuth, Aswin Gunasekar, Srinivasa Rao Gutta, Ajay Naini	A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Gordon Wan, Xiangli Li, Gennadiy Agranov, Marc Levoy, Mark Horowitz	CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan	A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Chulbum Kim, Jinho Ryu, Tae-Sung Lee, Hyunggon Kim, Jaewoo Lim, Jaeyong Jeong, Seonghwan Seo, Hongsoo Jeon, Bokeun Kim, Inyoul Lee, Dooseop Lee, Pansuk Kwak, Seongsoon Cho, Yongsik Yim, Changhyun Cho, Woopyo Jeong, Kwang-Il Park, Jin-Man Han, Duheon Song, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun	A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Mohammad K. Alghamdi, Anas A. Hamoui	A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a ΔΣ-Modulator Controller With a Scalable Sampling Frequency.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda	A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Fred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic	Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Debopriyo Chowdhury, Siva V. Thyagarajan, Lu Ye, Elad Alon, Ali M. Niknejad	A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Jaewook Shin, Hyunchol Shin	A 1.9-3.8 GHz ΔΣ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert Houle, Steve Lamphier, Carl Radens, Adnan Seferagic	A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Seulki Lee, Long Yan, Taehwan Roh, Sunjoo Hong, Hoi-Jun Yoo	A 75 µ W Real-Time Scalable Body Area Network Controller and a 25 µW ExG Sensor IC for Compact Sleep Monitoring Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Makoto Nagata, Vivek De	Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Donggu Im, Hongteuk Kim, Kwyro Lee	A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Fridolin Michel, Michiel Steyaert	A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Tarek Zaki, Frederik Ante, Ute Zschieschang, Joerg Butschke, Florian Letzkus, Harald Richter, Hagen Klauk, Joachim N. Burghartz	A 3.3 V 6-Bit 100 kS/s Current-Steering Digital-to-Analog Converter Using Organic P-Type Thin-Film Transistors on Glass.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Young Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim	A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Matteo Crotti, Ivan Rech, Massimo Ghioni	Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	François Belmas, Frédéric Hameau, Jean-Michel Fournier	A Low Power Inductorless LNA With Double ${\rm G} _{\rm m}$ Enhancement in 130 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Sang-Young Kim, Gabriel M. Rebeiz	A Low-Power BiCMOS 4-Element Phased Array Receiver for 76-84 GHz Radars and Communication Systems.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi	Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi	A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Shyuan Liao, Yen-Shuo Chang, Chia-Hsin Wu, Hung-Chieh Tsai, Hsin-Hua Chen, Min Chen, Ching-Wen Hsueh, Jian-Bang Lin, Den-Kai Juang, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chih-Heng Shih, Barry Hong, Heng-Ruey Hsu, Chih-Yuan Wang, Meng-Shiang Lin, Wei-Hsiang Tseng, Che-Hsiung Yang, Lawrence Chen Lee, Ting-Jyun Jheng, Wen-Wei Yang, Ming-Yang Chao, Jyh-Shin Pan	A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno	A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Diptendu Ghosh, Ranjit Gharpurey	A Power-Efficient Receiver Architecture Employing Bias-Current-Shared RF and Baseband With Merged Supply Voltage Domains and 1/f Noise Reduction.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Wei-Te Lin, Tai-Haur Kuo	A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yuyu Chang, John C. Leete, Zhimin Zhou, Morteza Vadipour, Yin-Ting Chang, Hooman Darabi	A Differential Digitally Controlled Crystal Oscillator With a 14-Bit Tuning Resolution and Sine Wave Outputs for Cellular Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung	A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Wonyoung Kim, David Brooks, Gu-Yeon Wei	A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Chintan Thakkar, Lingkai Kong, Kwangmo Jung, Antoine Frappe, Elad Alon	A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan	A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Frank Van de Sande, Nico Lugil, Filip Demarsin, Zeger Hendrix, Alvin Andries, Peter Brandt, William Anklam, Jeffery S. Patterson, Brian Miller, Michael Rytting, Mike Whaley, Bob Jewett, Jacky Liu, Jake Wegman, Ken Poulton	A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz fT BiCMOS Process.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Vivienne Sze, Anantha P. Chandrakasan	A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Jing Guo, George Jie Yuan, Jiageng Huang, Jessica Ka-Yan Law, Chi-Kong Yeung, Mansun Chan	32.9 nV/rt Hz ${-}$60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno	A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii	An Embedded DRAM Technology for High-Performance NAND Flash Memories.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Jianhua Lu, Ning-Yi Wang, Mau-Chung Frank Chang	A Compact and Low Power 5-10 GHz Quadrature Local Oscillator for Cognitive Radio Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Simone Gambini, John Crossley, Elad Alon, Jan M. Rabaey	A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Un-Ku Moon	New Associate Editors.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Marc Tiebout, Hans-Dieter Wohlmuth, Herbert Knapp, Raffaele Salerno, Michael Druml, Mirjana Rest, Johann Kaeferboeck, Johann Wuertele, Sherif Sayed Ahmed, Andreas Schiessl, Ralf Juenemann, Anna Zielska	Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf	A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	E.-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang	Power Optimized ADC-Based Serial Link Receiver.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Matthew Loh, Azita Emami-Neyestanak	A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Mehran M. Izad, Chun-Huat Heng	A Pulse Shaping Technique for Spur Suppression in Injection-Locked Synthesizers.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa	A 21 nV/√ Hz Chopper-Stabilized Multi-Path Current-Feedback Instrumentation Amplifier With 2 µ V Offset.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Kris Myny, Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans	An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Laurent Negre, David Roy, Florian Cacho, Patrick Scheer, Sebastien Jan, Samuel Boret, Daniel Gloria, Gérard Ghibaudo	Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Albert Wang, Alyosha Molnar	A Light-Field Image Sensor in 180 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu	Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo	A 0.24-nJ/b Wireless Body-Area-Network Transceiver With Scalable Double-FSK Modulation.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic	Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro	A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Muhammad Hassan, Lawrence E. Larson, Vincent W. Leung, Peter Asbeck	A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Paul Peng Liu, Karl Skucha, Yida Duan, Mischa Megens, Jungkyu Kim, Igor I. Izyumin, Simone Gambini, Bernhard E. Boser	Magnetic Relaxation Detector for Microbead Labels.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Luis A. Camuñas-Mesa, Carlos Zamarreño-Ramos, Alejandro Linares-Barranco, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Ward S. Titus, John G. Kenney	A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara	A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Niklas Lotze, Yiannos Manoli	A 62 mV 0.13 µ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai	A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Xicheng Jiang, Jungwoo Song, Jianlong Chen, Vinay Chandrasekhar, Sherif Galal, Felix Y. L. Cheung, Darwin Cheung, Todd Brooks	A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 $\mu$m CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Shinichiro Uemura, Yukio Hiraoka, Takayuki Kai, Shiro Dosho	Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi	Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang	A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Tzu-Chi Huang, Chun-Yu Hsieh, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Ming-Wei Lee	A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Federico Guanziroli, Rossella Bassoli, Carlo Crippa, Daniele Devecchi, Germano Nicollini	A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Marcelo Yuffe, Moty Mehalel, Ernest Knoll, Joseph Shor, Tsvika Kurts, Eran Altshuler, Eyal Fayneh, Kosta Luria, Michael Zelikson	A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Toshifumi Nakatani, Jeremy Rode, Donald Kimball, Lawrence E. Larson, Peter Asbeck	Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman	Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF

Publications at "J. Solid-State Circuits"( http://dblp.L3S.de/Venues/J._Solid-State_Circuits )