Search results for "Jaan Raik"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik	Automated correction of design errors by edge redirection on High-Level Decision Diagrams.	ISQED	2012	DBLP DOI BibTeX RDF
1	Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov	Automated test bench generation for high-level synthesis flow ABELITE.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara	Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee	Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations.	DFT	2011	DBLP DOI BibTeX RDF
1	Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus (eds.)	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011	DDECS	2011	DBLP BibTeX RDF
1	Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik	Probabilistic equivalence checking based on high-level decision diagrams.	DDECS	2011	DBLP DOI BibTeX RDF
1	Sergei Kostin, Raimund Ubar, Jaan Raik	Defect-oriented module-level fault diagnosis in digital circuits.	DDECS	2011	DBLP DOI BibTeX RDF
1	Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik	Evolutionary Approach to Test Generation for Functional BIST	CoRR	2010	DBLP BibTeX RDF
1	Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman	Structural fault collapsing by superposition of BDDs for test generation in digital circuits.	ISQED	2010	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits.	DELTA	2010	DBLP DOI BibTeX RDF	extended fault classes, parallel exact critical path tracing, fault simulation, digital circuits, fault analysis
1	Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova	An approach for PSL assertion coverage analysis with high-level decision diagrams.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits.	DSD	2010	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Parallel X-fault simulation with critical path tracing technique.	DATE	2010	DBLP BibTeX RDF
1	Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman	Fault collapsing with linear complexity in digital circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko	Constraint-based test pattern generation at the Register-Transfer Level.	DDECS	2010	DBLP DOI BibTeX RDF
1	Jaan Raik, Vineeth Govind, Raimund Ubar	Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar	PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams.	J. Electronic Testing	2009	DBLP BibTeX RDF
1	Raimund Ubar, Sergei Kostin, Jaan Raik	Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems.	DSD	2009	DBLP DOI BibTeX RDF
1	Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman	Structurally synthesized multiple input BDDs for simulation of digital circuits.	ICECS	2009	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Kostin, Jaan Raik	Embedded fault diagnosis in digital systems with BIST.	Microprocessors and Microsystems - Embedded Hardware Design	2008	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin	Mixed hierarchical-functional fault models for targeting sequential cores.	Journal of Systems Architecture - Embedded Systems Design	2008	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.	DELTA	2008	DBLP DOI BibTeX RDF	high-level decision diagrams, fault tolerance, fault simulation
1	Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.	DSD	2008	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar	Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation.	European Test Symposium	2008	DBLP DOI BibTeX RDF	assertion checking, decision diagrams, Property Specification Language
1	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Parallel fault backtracing for calculation of fault coverage.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Eero Ivask, Jaan Raik, Raimund Ubar	Distributed Approach for Genetic Test Generation in the Field of Digital Electronics.	IDC	2008	DBLP DOI BibTeX RDF
1	Eero Ivask, Jaan Raik, Raimund Ubar	Web-Based Framework for Parallel Distributed Test.	DDECS	2008	DBLP DOI BibTeX RDF
1	Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee	Code Coverage Analysis using High-Level Decision Diagrams.	DDECS	2008	DBLP DOI BibTeX RDF
1	Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar	FPGA-based fault emulation of synchronous sequential circuits.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen	Fault Diagnosis in Integrated Circuits with BIST.	DSD	2007	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus	Hierarchical Identification of Untestable Faults in Sequential Circuits.	DSD	2007	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar, Vineeth Govind	Test Configurations for Diagnosing Faulty Links in NoC Switches.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski	Layout to Logic Defect Analysis for Hierarchical Test Generation.	DDECS	2007	DBLP BibTeX RDF
1	Jaan Raik, Raimund Ubar, Taavi Viilukas	High-Level Decision Diagram based Fault Models for Targeting FSMs.	DSD	2006	DBLP DOI BibTeX RDF
1	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
1	Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar	Improved Fault Emulation for Synchronous Sequential Circuits.	DSD	2005	DBLP DOI BibTeX RDF
1	Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov	An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform.	DSD	2005	DBLP DOI BibTeX RDF
1	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.	DSD	2005	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman	Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs.	EDCC	2005	DBLP DOI BibTeX RDF
1	Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe	Evaluating Fault Emulation on FPGA.	FPL	2004	DBLP DOI BibTeX RDF
1	Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider	Web-Based Environment for Digital Electronics Test Tools.	Virtual Enterprises and Collaborative Networks	2004	DBLP BibTeX RDF
1	T. Cibáková, María Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar	Hierarchical test generation for combinational circuits with real defects coverage.	Microelectronics Reliability	2002	DBLP DOI BibTeX RDF
1	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik	Multi-Level Fault Simulation of Digital Systems on Decision Diagrams.	DELTA	2002	DBLP DOI BibTeX RDF	register transfer and gate level descriptions, fault simulation, decision diagrams, Digital systems
1	André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová	Internet-Based Collaborative Test Generation with MOSCITO.	DATE	2002	DBLP DOI BibTeX RDF
1	Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar	Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement.	Microelectronics Reliability	2001	DBLP DOI BibTeX RDF
1	Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar	Defect-Oriented Fault Simulation and Test Generation in Digital Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar	Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams
1	Raimund Ubar, Jaan Raik	Efficient Hierarchical Approach to Test Generation for Digital Systems.	ISQED	2000	DBLP DOI BibTeX RDF
1	Adam Morawiec, Raimund Ubar, Jaan Raik	Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams.	DATE	2000	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar	Sequential Circuit Test Generation Using Decision Diagram Models.	DATE	1999	DBLP DOI BibTeX RDF
1	Raimund Ubar, Jaan Raik, Adam Morawiec	Cycle-based Simulation with Decision Diagrams.	DATE	1999	DBLP DOI BibTeX RDF
1	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar	Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	Alternative Graphs, Malicious Fault List, VHDL, Fault Injection

Publications of "Jaan Raik" ( http://dblp.L3S.de/Authors/Jaan_Raik )