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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 7 keywords
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Results
Found 15 publication records. Showing 15 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy |
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V.  |
IEEE Trans. VLSI Syst.  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy |
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. |
ISLPED |
2011 |
DBLP BibTeX RDF |
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| 1 | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy |
Self-Repairing SRAM Using On-Chip Detection and Compensation. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim |
Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. |
CICC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang |
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. |
Microelectronics Reliability |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy |
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Design, yield, failure, SRAM, variation |
| 1 | Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown |
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy |
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy |
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Ik Joon Chang, Jae-Joon Kim, Kaushik Roy |
Robust level converter design for sub-threshold logic. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
low power circuit design, sub-threshold logic, level converter |
| 1 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy |
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy |
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
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