Search results for "Jai-Ming Lin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jai-Ming Lin, Zhi-Xiong Hung	SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang	Routability-driven placement algorithm for analog integrated circuits.	ISPD	2012	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu	Voltage island-driven floorplanning considering level shifter placement.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Zhi-Xiong Hung	UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang	Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.	DAC	2011	DBLP DOI BibTeX RDF
1	Jia-Ru Chuang, Jai-Ming Lin	Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang	Performance-driven analog placement considering boundary constraint.	DAC	2010	DBLP DOI BibTeX RDF	analog placement, boundary constraint, symmetry
1	Jai-Ming Lin, Hsi Hung	UFO: unified convex optimization algorithms for fixed-outline floorplanning.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Yao-Wen Chang	TCG: A transitive closure graph-based representation for general floorplans.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang	Placement with symmetry constraints for analog layout design using TCG-S.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Yao-Wen Chang	TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin	Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang	Performance-driven placement for dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	field-programmable gate array, placement, dynamically reconfigurable, layout, Computer-aided design of VLSI
1	Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang	Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Yao-Wen Chang	TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.	DAC	2002	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang	Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.	DATE	2002	DBLP DOI BibTeX RDF
1	Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong	Matching-based algorithm for FPGA channel segmentation design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang	Generic ILP-based approaches for time-multiplexed FPGA partitioning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Jai-Ming Lin, Yao-Wen Chang	TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.	DAC	2001	DBLP DOI BibTeX RDF
1	Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang	Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.	ICCD	2001	DBLP BibTeX RDF
1	Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang	An Algorithm for Dynamically Reconfigurable FPGA Placement.	ICCD	2001	DBLP BibTeX RDF
1	Yao-Wen Chang, Jai-Ming Lin, D. F. Wong	Graph matching-based algorithms for FPGA segmentation design.	ICCAD	1998	DBLP DOI BibTeX RDF

Publications of "Jai-Ming Lin" ( http://dblp.L3S.de/Authors/Jai-Ming_Lin )