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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 57 occurrences of 42 keywords
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Results
Found 61 publication records. Showing 61 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
Computer Generation of Hardware for Linear Digital Signal Processing Transforms.  |
ACM Trans. Design Autom. Electr. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Papamichael, James C. Hoe |
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai |
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe |
Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu |
Automatic Pipelining From Transactional Datapath Specifications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Papamichael, James C. Hoe, Onur Mutlu |
FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. |
NOCS |
2011 |
DBLP BibTeX RDF |
|
| 1 | Eric S. Chung, James C. Hoe, Ken Mai |
CoRAM: an in-fabric memory architecture for FPGA-based computing. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi |
The Future of Architectural Simulation. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric S. Chung, James C. Hoe |
High-Level Design and Validation of the BlueSPARC Multithreaded Processor. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Yu, Tsuhan Chen, Franz Franchetti, James C. Hoe |
High Performance Stereo Vision Designed for Massively Data Parallel Platforms. |
IEEE Trans. Circuits Syst. Video Techn. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
Hardware implementation of the discrete fourier transform with non-power-of-two problem size. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | James C. Hoe, Vikram S. Adve (eds.) |
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010 |
ASPLOS |
2010 |
DBLP BibTeX RDF |
|
| 1 | Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai |
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? |
MICRO |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam |
Automatic multithreaded pipeline synthesis from transactional datapath specifications. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
automatic pipelining, datapath specification, design exploration of x86 processor pipelines, multithreading, hardware synthesis |
| 1 | Wei Yu, Franz Franchetti, James C. Hoe, Yao-Jen Chang, Tsuhan Chen |
Fast bilateral filtering by adapting block size. |
ICIP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu |
Automatic pipelining from transactional datapath specifications. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Markus Püschel, Peter A. Milder, James C. Hoe |
Permuting streaming data using RAMs. |
J. ACM |
2009 |
DBLP DOI BibTeX RDF |
data reordering, linear bit mapping, streaming datapath, stride permutation, Permutation, switch, RAM, connection network, matrix transposition |
| 1 | Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi |
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. |
TRETS |
2009 |
DBLP DOI BibTeX RDF |
simulator, FPGA, prototype, multiprocessor, multicore, emulator |
| 1 | Brian T. Gold, Babak Falsafi, James C. Hoe |
Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors. |
PRDC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric S. Chung, James C. Hoe |
Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation. |
MEMOCODE |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Forrest Brewer, James C. Hoe |
2009 MEMOCODE Co-Design Contest. |
MEMOCODE |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Yu, Tsuhan Chen, James C. Hoe |
Real time stereo vision using exponential step cost aggregation on GPU. |
ICIP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe |
Dependable VLSI: device, design and architecture: how should they cooperate? |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter A. Milder, James C. Hoe, Markus Püschel |
Automatic generation of streaming datapaths for arbitrary fixed permutations. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | James C. Hoe, Jens Palsberg |
MEMOCODE 2006 guest editors' introduction. |
Design Autom. for Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Schaumont, Krste Asanovic, James C. Hoe |
MEMOCODE 2008 Co-Design Contest. |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Franz Franchetti, Yevgen Voronenko, Peter A. Milder, Srinivas Chellappa, Marek R. Telgarsky, Hao Shen, Paolo D'Alberto, Frédéric de Mesmay, James C. Hoe, José M. F. Moura, Markus Püschel |
Domain-specific library generation for parallel software and hardware platforms. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
Formal datapath representation and manipulation for implementing DSP transforms. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
high-level synthesis, streaming, discrete Fourier transform, linear transform |
| 1 | Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai |
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
simulator, FPGA, prototype, multiprocessor, multicore, emulator |
| 1 | John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic |
RAMP: Research Accelerator for Multiple Processors. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, distributed systems, integration, parallel architectures, transactional memory, emulation, distributed-shared memory, hardware-software codesign, modeling of computer architecture |
| 1 | Peter Tummeltshammer, James C. Hoe, Markus Püschel |
Time-Multiplexed Multiple-Constant Multiplication. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe |
PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers. |
PRDC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Forrest Brewer, James C. Hoe |
MEMOCODE 2007 Co-Design Contest. |
MEMOCODE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai |
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe |
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson |
Generating FPGA-Accelerated DFT Libraries. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe |
Statistical sampling of microarchitecture simulation. |
ACM Trans. Model. Comput. Simul. |
2006 |
DBLP DOI BibTeX RDF |
Microarchitecture simulation, SPEC CPU2000 simulation, cold-start bias, simulation sampling, statistical sampling |
| 1 | Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe |
SimFlex: Statistical Sampling of Computer System Simulation. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
SimFlex, CPU, statistical sampling, SPEC, computer system simulation |
| 1 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe |
Simulation sampling with live-points. |
ISPASS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe |
Statistical sampling of microarchitecture simulation. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe |
Reunion: Complexity-Effective Multicore Redundancy. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel |
Fast and accurate resource estimation of automatically generated custom DFT IP cores. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
FPGA resource estimation, design generator, IP, discrete fourier transform |
| 1 | Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk |
TRUSS: A Reliable, Scalable Server Architecture. |
IEEE Micro |
2005 |
DBLP DOI BibTeX RDF |
and Fault-Tolerance, and Fault-Tolerance, Reliability, Reliability, Reliability, Testing, Testing, Testing and Fault-Tolerance, Performance Analysis and Design Aids |
| 1 | Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel |
Automatic generation of customized discrete fourier transform IPs. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
design generator, FPGA, IP, discrete fourier transform |
| 1 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe |
TurboSMARTS: accurate microarchitecture simulation sampling in minutes. |
SIGMETRICS |
2005 |
DBLP DOI BibTeX RDF |
checkpointed microarchitecture simulation, simulation sampling |
| 1 | Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk |
Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | James C. Hoe, Arvind |
Operation-centric hardware description and synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk |
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. |
SIGMETRICS Performance Evaluation Review |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Grace Nordin, James C. Hoe |
Synchronous extensions to operation centric hardware description languages. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk |
Fingerprinting: bounding soft-error detection latency and bandwidth. |
ASPLOS |
2004 |
DBLP DOI BibTeX RDF |
dual modular redundancy (DMR), error detection, soft errors, backwards error recovery (BER) |
| 1 | Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi |
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Tummeltshammer, James C. Hoe, Markus Püschel |
Multiple constant multiplication by time-multiplexed mapping of addition chains. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
multiplierless, fusion, directed acyclic graph, addition chains |
| 1 | Roland E. Wunderlich, James C. Hoe |
In-system FPGA prototyping of an itanium microarchitecture. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Püschel, Adam C. Zelinski, James C. Hoe |
Custom-optimized multiplierless implementations of DSP algorithms. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Roland E. Wunderlich, James C. Hoe |
In-System FPGA Prototyping of an Itanium Microarchitecture. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe |
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. (PDF / PS) |
ISCA |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Joydeep Ray, James C. Hoe |
High-level modeling and FPGA prototyping of microprocessors. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture |
| 1 | Joydeep Ray, James C. Hoe, Babak Falsafi |
Dual use of superscalar datapath for transient-fault detection and recovery. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | James C. Hoe, Arvind |
Synthesis of Operation-Centric Hardware Descriptions. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | James C. Hoe, Arvind |
Hardware Synthesis from Term Rewriting Systems. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
| 1 | Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton |
START-NG: Delivering Seamless Parallel Computing. |
Euro-Par |
1995 |
DBLP DOI BibTeX RDF |
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