Search results for "James H. Aylor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Mark A. Hanson, Harry C. Powell Jr., Adam T. Barth, Kyle Ringgenberg, Benton H. Calhoun, James H. Aylor, John Lach	Body Area Sensor Networks: Challenges and Opportunities.	IEEE Computer	2009	DBLP DOI BibTeX RDF
1	Zachary D. Buckner, Michael L. Reed, James H. Aylor	Antialiasing Encoder Interface With Sub-Nyquist Sampling.	IEEE T. Instrumentation and Measurement	2006	DBLP DOI BibTeX RDF
1	Doris L. Carver, Ronald G. Hoelzeman, James H. Aylor, Michael G. Hinchey	Special Issue Introduction: The IEEE Computer Society's 60th Anniversary.	IEEE Computer	2006	DBLP DOI BibTeX RDF	60th Anniversary Celebration, Software engineering, IEEE Computer Society
1	Murali K. Nethi, James H. Aylor	Advances in Modelling and Simulation of Large Parallel/distributed Systems.	Parallel Processing Letters	2005	DBLP DOI BibTeX RDF
1	Yong Ma, James H. Aylor	System Lifetime Optimization for Heterogeneous Sensor Networks with a Hub-Spoke Topology.	IEEE Trans. Mob. Comput.	2004	DBLP DOI BibTeX RDF
1	Robert H. Klenke, James H. Aylor	A Proposed Modeling Environment to Teach Performance Modeling and Hardware/Software Codesign to Senior Undergraduates.	MSE	2003	DBLP DOI BibTeX RDF
1	Jason J. Hein, James H. Aylor, Robert H. Klenke	Performance-Based System Design Education.	MSE	2003	DBLP DOI BibTeX RDF
1	James H. Aylor	The End of Computing Disciplines as We Know Them? (PDF / PS)	IEEE Computer	2002	DBLP DOI BibTeX RDF
1	James H. Aylor	EIC's Message: It has been a Great Ride!	IEEE Computer	2002	DBLP DOI BibTeX RDF
1	Gang Han, Robert H. Klenke, James H. Aylor	Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	crossbar interconnection networks, simulation, performance evaluation, modeling, Multicomputer systems
1	Robert H. Klenke, James H. Aylor, Moshe Meyassed, William W. Dungan	Interfaces for mixed-level simulation with sequential elements.	Journal of Systems Architecture	2001	DBLP DOI BibTeX RDF
1	James H. Aylor	Keep on Keepin' on. (PDF / PS)	IEEE Computer	2001	DBLP DOI BibTeX RDF
1	James H. Aylor	Can We Work Together? (PDF / PS)	IEEE Computer	2001	DBLP DOI BibTeX RDF
1	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
1	James H. Aylor	New Computer Departments Reflect our Changing Industry.	IEEE Computer	2000	DBLP DOI BibTeX RDF
1	Moshe Meyassed, Robert H. Klenke, James H. Aylor	Resolving unknown inputs in mixed-level simulation with sequential elements.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	James H. Aylor	Computer for the 21st Century.	IEEE Computer	1999	DBLP BibTeX RDF
1	Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf	Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory.	HPCA	1999	DBLP DOI BibTeX RDF
1	Sally A. McKee, Robert H. Klenke, Kenneth L. Wright, William A. Wulf, Maximo H. Salinas, James H. Aylor, Alan P. Baston	Smarter Memory: Improving Bandwidth for Streamed References.	IEEE Computer	1998	DBLP DOI BibTeX RDF
1	Robert M. McGraw, James H. Aylor, Robert H. Klenke	A Top-Down Design Environment for Developing Pipelined Datapaths.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
1	Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh	An Integrated Design Environment for Performance and Dependability Analysis.	DAC	1997	DBLP DOI BibTeX RDF
1	Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman	An analysis of fault partitioned parallel test generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Robert H. Klenke, James H. Aylor, Joseph M. Wolf	An analysis of fault partitioning algorithms for fault partitioned ATPG.	VTS	1996	DBLP DOI BibTeX RDF	fault partitioning algorithm, VLSI device, detected fault broadcasting, preprocessing time, parallel processing, parallel processing, VLSI, fault diagnosis, integrated circuit testing, ATPG, automatic testing, dynamic load balancing, NP complete problem, digital system, test vector generation
1	Sally A. McKee, Assaji Aluwihare, Benjamin H. Clark, Robert H. Klenke, Trevor C. Landon, Christopher W. Oliver, Maximo H. Salinas, Adam E. Szymkowiak, Kenneth L. Wright, William A. Wulf, James H. Aylor	Design and Evaluation of Dynamic Access Ordering Hardware.	International Conference on Supercomputing	1996	DBLP DOI BibTeX RDF
1	Robert M. McGraw, Moshe Meyassed, Robert H. Klenke, James H. Aylor, Ronald D. Williams	Refinement of system-level designs using hybrid modeling.	ICECCS	1995	DBLP DOI BibTeX RDF	system-level design refinement, complex system design, unified modeling methodology, top-down/bottom-up design methodology, modeling environment, behavioral components, high risk portions, simulation, simulation, modelling, systems analysis, product development, hybrid modeling, multi-level modeling
1	Sanjaya Kumar, James H. Aylor, Barry W. Johnson, William A. Wulf	Object-Oriented Techniques in Hardware Design.	IEEE Computer	1994	DBLP DOI BibTeX RDF
1	Sanjay Srinivasan, James H. Aylor	Digital Circuit Testing on a Network of Workstations.	ICPP	1994	DBLP BibTeX RDF
1	Sally A. McKee, Robert H. Klenke, Andrew J. Schwab, William A. Wulf, Steven A. Moyer, James H. Aylor, Charles Y. Hitchcock	Experimental Implementation of Dynamic Access Ordering.	HICSS	1994	DBLP BibTeX RDF
1	Sanjaya Kumar, James H. Aylor, Barry W. Johnson, William A. Wulf	A Framework for Hardware / Software Codesign.	IEEE Computer	1993	DBLP DOI BibTeX RDF
1	Maximo H. Salinas, Barry W. Johnson, James H. Aylor	Implementation-Independent Model of an Instruction Set Architecture in VHDL.	IEEE Design & Test of Computers	1993	DBLP DOI BibTeX RDF
1	Robert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan	Workstation Based Parallel Test Generation.	ITC	1993	DBLP DOI BibTeX RDF
1	Robert H. Klenke, Ronald D. Williams, James H. Aylor	Parallel-Processing Techniques for Automatic Test Pattern Generation.	IEEE Computer	1992	DBLP DOI BibTeX RDF
1	James H. Aylor, Raul Camposano, Michael A. Schuette, Wayne Wolf, Nam S. Woo	The Future of Embedded System Design.	ICCD	1992	DBLP BibTeX RDF
1	James H. Aylor, Roy L. Russo, Bruce Shriver	The Promise of the Next Decade (Guest Editors' Introduction).	IEEE Computer	1991	DBLP BibTeX RDF
1	Maximo H. Salinas, Barry W. Johnson, James H. Aylor	Implementation-Independent Model of an Instruction Set Architecture Using VHDL.	ICCD	1991	DBLP BibTeX RDF
1	Bany W. Johnson, James H. Aylor	Reliability and safety analysis in medical applications of computer technology.	CBMS	1988	DBLP DOI BibTeX RDF
1	Ronald Waxman, James H. Aylor, Erich Marschner	The VHSIC Hardware Description Language (IEEE Standard 1076): Language Features Revisited.	COMPCON	1988	DBLP BibTeX RDF

Publications of "James H. Aylor" ( http://dblp.L3S.de/Authors/James_H._Aylor )