Search results for "Jamison D. Collins"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Hong Jiang, Guei-Yuan Lueh, Thomas Piazza, Hong Wang 0003	Bothnia: a dual-personality extension to the Intel integrated graphics driver.	Operating Systems Review	2011	DBLP DOI BibTeX RDF
1	Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang 0003	AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
1	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
1	Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang 0003, Mark Horowitz	Processor Performance Modeling using Symbolic Simulation.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.	PACT	2008	DBLP DOI BibTeX RDF	ia32, on-chip integration, chip multiprocessor, heterogeneous
1	Michael D. Linderman, Jamison D. Collins, Hong Wang 0003, Teresa H. Y. Meng	Merge: a programming model for heterogeneous multi-core systems.	ASPLOS	2008	DBLP DOI BibTeX RDF	GPGPU, predicate dispatch, heterogeneous multi-core
1	Benjamin C. Lee, Jamison D. Collins, Hong Wang 0003, David Brooks	CPR: Composable performance regression for scalable multiprocessor models.	MICRO	2008	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.	PLDI	2007	DBLP DOI BibTeX RDF	GPU, openMP, heterogeneous multi-cores
1	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang 0003	Sequencer virtualization.	ICS	2007	DBLP DOI BibTeX RDF	virtualization, multi-cores, MIMD
1	Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang 0003, John Paul Shen	Multiple Instruction Stream Processor.	ISCA	2006	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen	Helper Threads via Virtual Multithreading.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen	Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform.	ASPLOS	2004	DBLP DOI BibTeX RDF	DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL
1	Jamison D. Collins, Dean M. Tullsen	Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003	Control Flow Optimization Via Dynamic Reconvergence Prediction.	MICRO	2004	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen	Pointer cache assisted prefetching.	MICRO	2002	DBLP DOI BibTeX RDF
1	Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen	Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.	HPCA	2002	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen	Runtime identification of cache conflict misses: The adaptive miss buffer.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	adaptive miss buffer, cache exclusion, prefetching, victim cache, Cache architecture, conflict misses
1	Jamison D. Collins, Hong Wang 0003, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen	Speculative precomputation: long-range prefetching of delinquent loads.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Dynamic speculative precomputation.	MICRO	2001	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen	Hardware Identification of Cache Conflict Misses. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF

Publications of "Jamison D. Collins" ( http://dblp.L3S.de/Authors/Jamison_D._Collins )