Search results for "Jason Cong"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman	Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system.	TACO	2012	DBLP DOI BibTeX RDF
1	Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong	Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.	ISQED	2012	DBLP DOI BibTeX RDF
1	Jason Cong	Transformation from ad hoc EDA to algorithmic EDA.	ISPD	2012	DBLP DOI BibTeX RDF
1	Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabhakar	Towards layout-friendly high-level synthesis.	ISPD	2012	DBLP DOI BibTeX RDF
1	Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang	An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang 0001, Bin Liu 0006, Raghu Prabhakar, Glenn Reinman, Marco Vitanza	Compilation and architecture support for customized vector instruction extension.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou	Platform characterization for Domain-Specific Computing.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong	An integrated and automated memory optimization flow for FPGA behavioral synthesis.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jianwen Chen, Jason Cong, Ming Yan, Yi Zou	FPGA-accelerated 3D reconstruction using compressive sensing.	FPGA	2012	DBLP DOI BibTeX RDF
1	Jason Cong, Bingjun Xiao	FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
1	Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou	Combining module selection and replication for throughput-driven streaming programs.	DATE	2012	DBLP BibTeX RDF
1	Yu-Ting Chen, Jason Cong, Hui Huang 0001, Bin Liu 0006, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman	Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.	DATE	2012	DBLP BibTeX RDF
1	Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong	Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Jason Cong, Wei Jiang, Bin Liu 0006, Yi Zou	Automatic memory partitioning and scheduling for throughput and power optimization.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Bin Liu 0006, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang	High-Level Synthesis for FPGAs: From Prototyping to Deployment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Hui Huang 0001, Wei Jiang	Pattern-Mining for Behavioral Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong	An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Jason Cong	Overview of Center for Domain-Specific Computing.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Glenn Reinman, Alex A. T. Bui, V. Sarkar	Customizable Domain-Specific Computing.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Muhuan Huang, Yi Zou	Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms.	FPL	2011	DBLP DOI BibTeX RDF	fluid registration, FPGA, HLS
1	Ming Yan, Jianwen Chen, Luminita A. Vese, John D. Villasenor, Alex A. T. Bui, Jason Cong	EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation.	ISVC	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj, Hui Huang 0001, Chunyue Liu, Glenn Reinman, Yi Zou	An energy-efficient adaptive hybrid cache.	ISLPED	2011	DBLP BibTeX RDF
1	Jason Cong, Guojie Luo, Yiyu Shi	Thermal-aware cell and through-silicon-via co-placement for 3D ICs.	DAC	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Hui Huang 0001, Chunyue Liu, Yi Zou	A reuse-aware prefetching scheme for scratchpad memory.	DAC	2011	DBLP DOI BibTeX RDF
1	Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang	An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza	Accelerating vision and navigation applications on a customizable platform.	ASAP	2011	DBLP DOI BibTeX RDF
1	Jason Cong	Era of customization and specialization.	ASAP	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou	Domain-specific processor with 3D integration for medical image processing.	ASAP	2011	DBLP DOI BibTeX RDF
1	Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong	Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong	Multilevel Granularity Parallelism Synthesis on FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Yi Zou	Resolving implicit barrier synchronizations in FPGA HLS (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Jason Cong, John Lee, Guojie Luo	A unified optimization framework for simultaneous gate sizing and placement under density constraints.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Peng Zhang, Yi Zou	Combined loop transformation and hierarchy allocation for data reuse optimization.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj	Assuring application-level correctness against soft errors.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Yuhui Huang, Bo Yuan	ATree-based topology synthesis for on-chip network.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang	The DIMM tree architecture: A high bandwidth and scalable memory system.	ICCD	2011	DBLP DOI BibTeX RDF
1	Yu-Ting Chen, Jason Cong, Glenn Reinman	HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Bin Liu 0006, Rupak Majumdar, Zhiru Zhang	Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Jason Cong, Puneet Gupta, John Lee	Evaluating Statistical Power Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng	Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Deming Chen, Jason Cong, Yiping Fan, Lu Wan	LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Robert K. Brayton, Jason Cong	NSF Workshop on EDA: Past, Present, and Future (Part 2).	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Robert K. Brayton, Jason Cong	NSF Workshop on EDA: Past, Present, and Future (Part 1).	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	EDA, design automation
1	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
1	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability.	DAC	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, FPGA lookup table
1	Jason Cong, Chunyue Liu, Glenn Reinman	ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	application-specific Network-on-Chip, deadlock-free routing
1	Jason Cong, Yi Zou	A Comparative Study on the Architecture Templates for Dynamic Nested Loops.	FCCM	2010	DBLP DOI BibTeX RDF
1	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
1	Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu 0006, Kirill Minkovich, Bo Yuan, Yi Zou	Accelerating Monte Carlo based SSTA using FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, monte carlo, SSTA
1	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
1	Jason Cong, Hui Huang 0001, Wei Jiang	A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis.	DATE	2010	DBLP BibTeX RDF
1	Jason Cong, Bin Liu 0006, Junjuan Xu	Coordinated resource optimization in behavioral synthesis.	DATE	2010	DBLP BibTeX RDF
1	Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon	Logic-on-logic 3D integration and placement.	3DIC	2010	DBLP DOI BibTeX RDF
1	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
1	Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang	Synthesis Algorithm for Application-Specific Homogeneous Processor Networks.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Yi Zou	FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation.	TRETS	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Wolfgang Rosenstiel	The Last Byte: The HLS tipping point.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Jason Cong	Customizable domain-specific computing.	FPL	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Bin Liu 0006, Zhiru Zhang	Behavior-level observability don't-cares and application to low-power behavioral synthesis.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, observability, behavioral synthesis
1	Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang, Jason Cong	A scalable micro wireless interconnect structure for CMPs.	MOBICOM	2009	DBLP DOI BibTeX RDF	on-chip wireless interconnection network, chip multiprocessors
1	Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam	Multiband RF-interconnect for reconfigurable network-on-chip communications.	SLIP	2009	DBLP DOI BibTeX RDF	fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor
1	Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach	From milliwatts to megawatts: system level power challenge.	DAC	2009	DBLP DOI BibTeX RDF	system level power, system design
1	Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork	Moore's Law: another casualty of the financial meltdown?	DAC	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Guojie Luo	A multilevel analytical placement for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Puneet Gupta, John Lee	On the futility of statistical power optimization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj, Bin Liu 0006, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou	Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization.	FCCM	2009	DBLP DOI BibTeX RDF	precision analysis, static analysis, bitwidth
1	Jason Cong, Karthik Gururaj, Guoling Han	Synthesis of reconfigurable high-performance multicore systems.	FPGA	2009	DBLP DOI BibTeX RDF	coprocessor synthesis, reconfigurable high-performance computing, design space exploration
1	Jason Cong, Karthik Gururaj, Bin Liu 0006, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou	Revisiting bitwidth optimizations.	FPGA	2009	DBLP DOI BibTeX RDF	fixed-poin, fpga, arithmetic, bitwidth
1	Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu	High-performance CUDA kernel execution on FPGAs.	ICS	2009	DBLP DOI BibTeX RDF	cuda programming model, fpga, high level synthesis, high performance computing, gpu, coarse grained parallelism
1	Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu	FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs.	SASP	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj	Energy efficient multiprocessor task scheduling under input-dependent variation.	DATE	2009	DBLP BibTeX RDF
1	Jason Cong, Yi Zou	Parallel multi-level analytical global placement on graphics processing units.	ICCAD	2009	DBLP BibTeX RDF
1	Tony F. Chan, Jason Cong, Eric Radke	A rigorous framework for convergent net weighting schemes in timing-driven placement.	ICCAD	2009	DBLP BibTeX RDF
1	Jason Cong, Bin Liu 0006, Zhiru Zhang	Scheduling with soft constraints.	ICCAD	2009	DBLP BibTeX RDF
1	Jason Cong, Wei Jiang, Bin Liu 0006, Yi Zou	Automatic memory partitioning and scheduling for throughput and power optimization.	ICCAD	2009	DBLP BibTeX RDF
1	Jason Cong, Albert Liu, Bin Liu 0006	A variation-tolerant scheduler for better than worst-case behavioral synthesis.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, variation, behavioral synthesis
1	Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong	Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.	JETC	2008	DBLP DOI BibTeX RDF	3D packing, microarchitecture, 3D integration, thermal
1	Yuan Xie, Jason Cong, Paul D. Franzon	Editorial: Special issue on 3D integrated circuits and microarchitectures.	JETC	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Min Xie	A Robust Mixed-Size Legalization and Detailed Placement Algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Guojie Luo, Eric Radke	Highly Efficient Gradient Computation for Density-Constrained Analytical Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Yuzheng Ding	FPGA Technology Mapping.	Encyclopedia of Algorithms	2008	DBLP DOI BibTeX RDF
1	Jason Cong, John Lee, Lieven Vandenberghe	Robust gate sizing via mean excess delay minimization.	ISPD	2008	DBLP DOI BibTeX RDF	robust gate sizing, process variation, geometric programming, conditional value-at-risk
1	M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman	RF interconnects for communications on-chip.	ISPD	2008	DBLP DOI BibTeX RDF	RF-interconnect, network-on-chip, chip multiprocessors
1	Jason Cong, Guojie Luo	Highly efficient gradient computation for density-constrained analytical placement methods.	ISPD	2008	DBLP DOI BibTeX RDF	force-directed method, mixed-size placement
1	M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam	Power reduction of CMP communication networks via RF-interconnects.	MICRO	2008	DBLP DOI BibTeX RDF
1	Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong	Scheduling with integer time budgeting for low-power optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Wei Jiang	Pattern-based behavior synthesis for FPGA resource reduction.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, pattern, behavior synthesis
1	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
1	Kirill Minkovich, Jason Cong	Mapping for better than worst-case delays in LUT-based FPGA designs.	FPGA	2008	DBLP DOI BibTeX RDF	better than worst-case, razor, switching probabilities, simulation, logic synthesis, technology mapping, FPGA lookup table
1	Jason Cong, Junjuan Xu	Simultaneous FU and Register Binding Based on Network Flow Method.	DATE	2008	DBLP DOI BibTeX RDF
1	M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam	CMP network-on-chip overlaid with multi-band RF-interconnect.	HPCA	2008	DBLP DOI BibTeX RDF
1	Jason Cong	A new generation of C-base synthesis tool and domain-specific computing.	SoCC	2008	DBLP DOI BibTeX RDF
1	Amit Agarwal, Jason Cong, Brian Tagiku	Fault tolerant placement and defect reconfiguration for nano-FPGAs.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman	MC-Sim: an efficient simulation tool for MPSoC designs.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski	Accelerating Sequential Applications on CMPs Using Core Spilling.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF
1	Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden	Routability-Driven Placement and White Space Allocation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jason Cong, Kirill Minkovich	Optimality Study of Logic Synthesis for LUT-Based FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining

Publications of "Jason Cong" ( http://dblp.L3S.de/Authors/Jason_Cong )