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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 265 occurrences of 143 keywords
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Results
Found 335 publication records. Showing 335 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chunhua Xiao, M.-C. Frank Chang, Jason Cong, Michael Gill, Zhangqin Huang, Chunyue Liu, Glenn Reinman, Hao Wu |
Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects.  |
TACO  |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Agarwal, Jason Cong, Brian Tagiku |
The survivability of design-specific spare placement in FPGA architectures with high defect rates. |
ACM Trans. Design Autom. Electr. Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Guojie Luo, Yiyu Shi, Jason Cong |
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao |
Optimizing routability in large-scale mixed-size placement. |
ASP-DAC |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Louis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong |
Polyhedral-based data reuse optimization for configurable computing. |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong |
Improving high level synthesis optimization opportunity through polyhedral transformations. |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Muhuan Huang, Peng Zhang |
Efficient system-level mapping from streaming applications to FPGAs (abstract only). |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bingjun Xiao |
Defect recovery in nanodevice-based programmable interconnects (abstract only). |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaughn Betz, Jason Cong |
Are FPGAs suffering from the innovator's dilemna? |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj |
Architecture support for custom instructions with memory operations. |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong |
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman |
Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. |
TACO |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanghyo Kim, Sai-Wang Tam, Gyungsu Byun, Hao Wu, Lan Nan, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang |
Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang |
Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwen Chen, Jason Cong, Luminita A. Vese, John D. Villasenor, Ming Yan, Yi Zou |
A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj, Peng Zhang, Yi Zou |
Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. |
J. Electrical and Computer Engineering |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong |
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bo Yuan |
Energy-efficient scheduling on heterogeneous multi-core architectures. |
ISLPED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Ting Chen, Jason Cong, Hui Huang 0001, Chunyue Liu, Raghu Prabhakar, Glenn Reinman |
Static and dynamic co-optimizations for blocks mapping in hybrid caches. |
ISLPED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman |
BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs. |
ISLPED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman |
CHARM: a composable heterogeneous accelerator-rich microprocessor. |
ISLPED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang |
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. |
CICC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong |
Transformation from ad hoc EDA to algorithmic EDA. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabhakar |
Towards layout-friendly high-level synthesis. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Peng Zhang, Yi Zou |
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. |
DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu |
A metric for layout-friendly microarchitecture optimization in high-level synthesis. |
DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman |
Architecture support for accelerator-rich CMPs. |
DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanghyo Kim, Gyungsu Byun, Adrian Tang 0002, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang |
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang 0001, Bin Liu 0006, Raghu Prabhakar, Glenn Reinman, Marco Vitanza |
Compilation and architecture support for customized vector instruction extension. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou |
Platform characterization for Domain-Specific Computing. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong |
An integrated and automated memory optimization flow for FPGA behavioral synthesis. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwen Chen, Jason Cong, Ming Yan, Yi Zou |
FPGA-accelerated 3D reconstruction using compressive sensing. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bingjun Xiao |
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou |
Combining module selection and replication for throughput-driven streaming programs. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yu-Ting Chen, Jason Cong, Hui Huang 0001, Bin Liu 0006, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman |
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu, Raghu Prabhakar, Peng Zhang |
A Study on the Impact of Compiler Optimizations on High-Level Synthesis. |
LCPC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong |
Memory partitioning and scheduling co-optimization in behavioral synthesis. |
ICCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Alina Simion Sbîrlea, Yi Zou, Zoran Budimlic, Jason Cong, Vivek Sarkar |
Mapping a data-flow programming model onto heterogeneous platforms. |
LCTES |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang 0002, Xianlong Hong, Jason Cong |
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, Wei Jiang, Bin Liu 0006, Yi Zou |
Automatic memory partitioning and scheduling for throughput and power optimization. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu 0006, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang |
High-Level Synthesis for FPGAs: From Prototyping to Deployment. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Hui Huang 0001, Wei Jiang |
Pattern-Mining for Behavioral Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong |
An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong |
Overview of Center for Domain-Specific Computing. |
J. Comput. Sci. Technol. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Glenn Reinman, Alex A. T. Bui, Vivek Sarkar |
Customizable Domain-Specific Computing. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Muhuan Huang, Yi Zou |
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
fluid registration, FPGA, HLS |
| 1 | Ming Yan, Jianwen Chen, Luminita A. Vese, John D. Villasenor, Alex A. T. Bui, Jason Cong |
EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. |
ISVC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj, Hui Huang 0001, Chunyue Liu, Glenn Reinman, Yi Zou |
An energy-efficient adaptive hybrid cache. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, Guojie Luo, Yiyu Shi |
Thermal-aware cell and through-silicon-via co-placement for 3D ICs. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Hui Huang 0001, Chunyue Liu, Yi Zou |
A reuse-aware prefetching scheme for scratchpad memory. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang |
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. |
ISSCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza |
Accelerating vision and navigation applications on a customizable platform. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong |
Era of customization and specialization. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou |
Domain-specific processor with 3D integration for medical image processing. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang 0002, Xianlong Hong, Jason Cong |
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong |
Multilevel Granularity Parallelism Synthesis on FPGAs. |
FCCM |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Yi Zou |
Resolving implicit barrier synchronizations in FPGA HLS (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Muhuan Huang, Yi Zou |
3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications. |
SASP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, John Lee, Guojie Luo |
A unified optimization framework for simultaneous gate sizing and placement under density constraints. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Peng Zhang, Yi Zou |
Combined loop transformation and hierarchy allocation for data reuse optimization. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj |
Assuring application-level correctness against soft errors. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Yuhui Huang, Bo Yuan |
ATree-based topology synthesis for on-chip network. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang |
The DIMM tree architecture: A high bandwidth and scalable memory system. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Ting Chen, Jason Cong, Glenn Reinman |
HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu 0006, Rupak Majumdar, Zhiru Zhang |
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Puneet Gupta, John Lee |
Evaluating Statistical Power Optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng |
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Deming Chen, Jason Cong, Yiping Fan, Lu Wan |
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert K. Brayton, Jason Cong |
NSF Workshop on EDA: Past, Present, and Future (Part 2). |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert K. Brayton, Jason Cong |
NSF Workshop on EDA: Past, Present, and Future (Part 1). |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
EDA, design automation |
| 1 | Jason Cong, Guojie Luo |
An analytical placer for mixed-size 3D placement. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
placement, 3D integration, analytical method |
| 1 | Jason Cong, Kirill Minkovich |
LUT-based FPGA technology mapping for reliability. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
logic synthesis, error analysis, windowing, technology mapping, don't cares, FPGA lookup table |
| 1 | Jason Cong, Chunyue Liu, Glenn Reinman |
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
application-specific Network-on-Chip, deadlock-free routing |
| 1 | Jason Cong, Yi Zou |
A Comparative Study on the Architecture Templates for Dynamic Nested Loops. |
FCCM |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Kirill Minkovich |
LUT-based FPGA technology mapping for reliability (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table |
| 1 | Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu 0006, Kirill Minkovich, Bo Yuan, Yi Zou |
Accelerating Monte Carlo based SSTA using FPGA. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
FPGA, monte carlo, SSTA |
| 1 | Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong |
Bit-level optimization for high-level synthesis and FPGA-based acceleration. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
bit-level optimization, fpga, high-level synthesis |
| 1 | Jason Cong, Hui Huang 0001, Wei Jiang |
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu 0006, Junjuan Xu |
Coordinated resource optimization in behavioral synthesis. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon |
Logic-on-logic 3D integration and placement. |
3DIC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Yiping Fan, Junjuan Xu |
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
distributed register file, Behavioral synthesis, resource binding |
| 1 | Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang |
Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Yi Zou |
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. |
TRETS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Wolfgang Rosenstiel |
The Last Byte: The HLS tipping point. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong |
Customizable domain-specific computing. |
FPL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu 0006, Zhiru Zhang |
Behavior-level observability don't-cares and application to low-power behavioral synthesis. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
low power, observability, behavioral synthesis |
| 1 | Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang 0001, Jason Cong |
A scalable micro wireless interconnect structure for CMPs. |
MOBICOM |
2009 |
DBLP DOI BibTeX RDF |
on-chip wireless interconnection network, chip multiprocessors |
| 1 | Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam |
Multiband RF-interconnect for reconfigurable network-on-chip communications. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor |
| 1 | Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach |
From milliwatts to megawatts: system level power challenge. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
system level power, system design |
| 1 | Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork |
Moore's Law: another casualty of the financial meltdown? |
DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Guojie Luo |
A multilevel analytical placement for 3D ICs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Puneet Gupta, John Lee |
On the futility of statistical power optimization. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj, Bin Liu 0006, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou |
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. |
FCCM |
2009 |
DBLP DOI BibTeX RDF |
precision analysis, static analysis, bitwidth |
| 1 | Jason Cong, Karthik Gururaj, Guoling Han |
Synthesis of reconfigurable high-performance multicore systems. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
coprocessor synthesis, reconfigurable high-performance computing, design space exploration |
| 1 | Jason Cong, Karthik Gururaj, Bin Liu 0006, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou |
Revisiting bitwidth optimizations. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fixed-poin, fpga, arithmetic, bitwidth |
| 1 | Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu |
High-performance CUDA kernel execution on FPGAs. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
cuda programming model, fpga, high level synthesis, high performance computing, gpu, coarse grained parallelism |
| 1 | Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu |
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. |
SASP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Karthik Gururaj |
Energy efficient multiprocessor task scheduling under input-dependent variation. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, Yi Zou |
Parallel multi-level analytical global placement on graphics processing units. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Tony F. Chan, Jason Cong, Eric Radke |
A rigorous framework for convergent net weighting schemes in timing-driven placement. |
ICCAD |
2009 |
DBLP BibTeX RDF |
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