Search results for "Jason Helge Anderson"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Marcel Gort, Jason Helge Anderson	Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Qiang Wang, Chirag Ravishankar	Raising FPGA Logic Density Through Synthesis-Inspired Architecture.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Warren Wai-Kit Shum, Jason Helge Anderson	Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power.	FPGA	2012	DBLP DOI BibTeX RDF
1	Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson	The VTR project: architecture and CAD for FPGAs from verilog to routing.	FPGA	2012	DBLP DOI BibTeX RDF
1	Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski	Impact of FPGA architecture on resource sharing in high-level synthesis.	FPGA	2012	DBLP DOI BibTeX RDF
1	Bill Teng, Jason Helge Anderson	Latch-Based Performance Optimization for FPGAs.	FPL	2011	DBLP DOI BibTeX RDF
1	Marcel Gort, Jason Helge Anderson	Reducing FPGA Router Run-Time through Algorithm and Architecture.	FPL	2011	DBLP DOI BibTeX RDF	fast CAD, scalable CAD, fast routing, FPGA, routing, CAD, SAT, Boolean Satisfiability, run-time, runtime, PathFinder
1	Warren Wai-Kit Shum, Jason Helge Anderson	FPGA glitch power analysis and reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis	Low-cost hardware profiling of run-time and energy in FPGA embedded processors.	ASAP	2011	DBLP DOI BibTeX RDF
1	Alireza Rakhshanfar, Jason Helge Anderson	An integer programming placement approach to FPGA clock power reduction.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Qiang Wang	Area-efficient FPGA logic elements: Architecture and synthesis.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jason Luu, Jason Helge Anderson, Jonathan Rose	Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect.	FPGA	2011	DBLP DOI BibTeX RDF
1	Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski	LegUp: high-level synthesis for FPGA-based processor/accelerator systems.	FPGA	2011	DBLP DOI BibTeX RDF
1	Steven Birk, J. Gregory Steffan, Jason Helge Anderson	Parallelizing FPGA placement using Transactional Memory.	FPT	2010	DBLP DOI BibTeX RDF
1	Marcel Gort, Jason Helge Anderson	Deterministic multi-core parallel routing for FPGAs.	FPT	2010	DBLP DOI BibTeX RDF
1	Jason Helge Anderson	A PUF design for secure FPGA-based embedded systems.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
1	Jason Helge Anderson, Farid N. Najm	Low-Power Programmable FPGA Routing Circuitry.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson	Packing Techniques for Virtex-5 FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Qiang Wang	Improving logic density through synthesis-inspired architecture.	FPL	2009	DBLP DOI BibTeX RDF
1	Safeen Huda, Muntasir Mallick, Jason Helge Anderson	Clock gating architectures for FPGA power reduction.	FPL	2009	DBLP DOI BibTeX RDF
1	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
1	Jason Helge Anderson	Emerging application domains: research challenges and opportunities for FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	performance, field-programmable gate array, fpga, applications, high-performance computing, power, reconfigurable computing
1	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
1	Jason Helge Anderson, Farid N. Najm	Active leakage power optimization for FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Farid N. Najm	Power estimation techniques for FPGAs.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng	Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.	FPL	2004	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Farid N. Najm	Interconnect capacitance estimation for FPGAs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Farid N. Najm, Tim Tuan	Active leakage power optimization for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	optimization, FPGAs, field-programmable gate arrays, low-power design, power, leakage
1	Jason Helge Anderson, Farid N. Najm	Low-power programmable routing circuitry for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Farid N. Najm	Switching activity analysis and pre-layout activity prediction for FPGAs.	SLIP	2003	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, power, estimation
1	Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman	A Placement Algorithm for FPGA Designs with Multiple I/O Standards.	FPL	2000	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Stephen Dean Brown	Technology Mapping for Large Complex PLDs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
1	Jason Helge Anderson, Stephen Dean Brown	An LPGA with Foldable PLA-style Logic Blocks.	FPGA	1998	DBLP DOI BibTeX RDF

Publications of "Jason Helge Anderson" ( http://dblp.L3S.de/Authors/Jason_Helge_Anderson )