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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9 occurrences of 7 keywords
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Results
Found 26 publication records. Showing 26 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Carlos González, Daniel Mozos, Javier Resano, Antonio Plaza |
FPGA Implementation of the N-FINDR Algorithm for Remotely Sensed Hyperspectral Image Analysis.  |
IEEE T. Geoscience and Remote Sensing  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Juan Antonio Clemente, Javier Resano, Carlos González, Daniel Mozos |
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Juan Antonio Clemente, Daniel Mozos, Javier Resano |
A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems. |
IPDPS Workshops |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos |
A task graph execution manager for reconfigurable multi-tasking systems. |
Microprocessors and Microsystems - Embedded Hardware Design |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Carlos González, Javier Resano, Daniel Mozos, Antonio Plaza, David Valencia |
FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis. |
EURASIP J. Adv. Sig. Proc. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Carlos González, Daniel Mozos, Javier Resano, Antonio Plaza |
FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images. |
ERSA |
2010 |
DBLP BibTeX RDF |
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| 1 | Javier Olivito, Carlos González, Javier Resano |
FPGA implementation of a strong Reversi player. |
FPT |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Carlos González, Daniel Mozos, Javier Resano |
FPGA support for satellite computations of hyper spectral images. |
FPL |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Juan Antonio Clemente, Carlos González, Daniel Mozos, Francky Catthoor |
Efficiently scheduling runtime reconfigurations. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
hardware multitasking, runtime/design-time scheduling, FPGAs, Reconfigurable architectures |
| 1 | Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos |
A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Hardware multitasking, FPGAs, Reconfigurable architectures, Task scheduling |
| 1 | Javier Resano, Daniel Mozos, Francky Catthoor |
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware |
CoRR |
2007 |
DBLP BibTeX RDF |
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| 1 | Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor |
Memory hierarchy for high-performance and energyaware reconfigurable systems. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Juan Antonio Clemente, Carlos González, Jose Luis Garcia, Daniel Mozos |
HW implementation of an execution manager for reconfigurable systems. |
ERSA |
2007 |
DBLP BibTeX RDF |
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| 1 | Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor |
Reducing the reconfiguration overhead: a survey of techniques. |
ERSA |
2007 |
DBLP BibTeX RDF |
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| 1 | Elena Perez Ramo, Javier Resano |
A Dual Cache for Performance and Energy Aware Reconfigurable HW. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor |
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor |
A Reconfiguration Manager for Dynamically Reconfigurable Hardware. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
Reconfigurable hardware, Real-time and embedded systems, Performance Analysis and Design Aids |
| 1 | Javier Resano, Daniel Mozos, Francky Catthoor |
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor |
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. |
Microprocessors and Microsystems |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano |
A Specific Scheduling Flow for Dynamically Reconfigurable Hardware. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Daniel Mozos |
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
dynamic reconfigurable hardware, run-time scheduling |
| 1 | Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién |
Analyzing communication overheads during hardware/software partitioning. |
Microelectronics Journal |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor |
Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién |
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor |
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. (PDF / PS) |
FCCM |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor |
Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. |
ESTImedia |
2003 |
DBLP BibTeX RDF |
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