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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3 occurrences of 3 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, L. John |
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue.  |
IEEE Micro  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John |
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.  |
PACT  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John |
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.  |
MICRO  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies.  |
ISCA  |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
| 1 | Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John |
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.  |
MICRO  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John |
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems.  |
HPCA  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. John |
Bank-aware Dynamic Cache Partitioning for Multicore Architectures.  |
ICPP  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John, Jeff Stuecheli, John Griswell, Paul Tu, Louis Capps, Anton Blanchard, Ravel Thai |
Automatic testcase synthesis and performance model validation for high performance PowerPC processors.  |
ISPASS  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile |
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.  |
IBM Journal of Research and Development  |
2002 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #9 of 9 (100 per page; Change: )
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