Search results for "Jianchao Lu"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link
1	Jianchao Lu, Xiaomi Mao, Baris Taskin	Integrated Clock Mesh Synthesis With Incremental Register Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Jianchao Lu, Ying Teng, Baris Taskin	A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock buffer polarity assignment with skew tuning.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Xiaomi Mao, Baris Taskin	Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis.	ISPD	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin	Steiner tree based rotary clock routing with bounded skew and capacitive load balancing.	DATE	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Yusuf Aksehir, Baris Taskin	Register On MEsh (ROME): A novel approach for clock mesh network synthesis.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ying Teng, Jianchao Lu, Baris Taskin	ROA-brick topology for rotary resonant clocks.	ICCD	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Post-CTS Delay Insertion.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock buffer polarity assignment considering capacitive load.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock Tree Synthesis with XOR Gates for Polarity Assignment.	ISVLSI	2010	DBLP DOI BibTeX RDF

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Publications of "Jianchao Lu" ( http://dblp.L3S.de/Authors/Jianchao_Lu )