Search results for "Jiang Hu"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jiang Hu, Cheng-Kok Koh	Guest Editorial Special Section on the 2011 International Symposium on Physical Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Jiang Hu, Cheng-Kok Koh (eds.)	International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012	ISPD	2012	DBLP BibTeX RDF
1	Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson, Jiang Hu	Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Yifang Liu, Jiang Hu	GPU-Based Parallelization for Fast Circuit Optimization.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Yifang Liu, Rupesh S. Shelar, Jiang Hu	Simultaneous Technology Mapping and Placement for Delay Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Kyu-Nam Shim, Jiang Hu	Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects.	ISQED	2011	DBLP DOI BibTeX RDF
1	Yao-Wen Chang, Jiang Hu (eds.)	Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011	ISPD	2011	DBLP BibTeX RDF
1	Xi Chen, Jiang Hu, Ning Xu	Regularity-constrained floorplanning for multi-core processors.	ISPD	2011	DBLP DOI BibTeX RDF
1	Yi-Le Huang, Jiang Hu, Weiping Shi	Lagrangian relaxation for gate implementation selection.	ISPD	2011	DBLP DOI BibTeX RDF
1	Yimei Kang, Guan Wang, Jiang Hu	A mean shift based small target tracking algorithm in colored video.	SoCPaR	2011	DBLP DOI BibTeX RDF
1	Muhammet Mustafa Ozdal, Steven Burns, Jiang Hu	Gate sizing and device technology selection algorithms for high-performance industrial designs.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu	Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Yifang Liu, Jiang Hu	A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li	Combinatorial Algorithms for Fast Clock Mesh Optimization.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Rupak Samanta, Jiang Hu, Peng Li	Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Shiyan Hu, Patrik Shah, Jiang Hu	Pattern Sensitive Placement Perturbation for Manufacturability.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu	Useful clock skew optimization under a multi-corner multi-mode design framework.	ISQED	2010	DBLP DOI BibTeX RDF
1	Kyu-Nam Shim, Jiang Hu, José Silva-Martínez	A dual-level adaptive supply voltage system for variation resilience.	ISQED	2010	DBLP DOI BibTeX RDF
1	Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li	Accurate clock mesh sizing via sequential quadraticprogramming.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, sequential quadratic programming
1	Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn	Detecting tangled logic structures in VLSI netlists.	DAC	2010	DBLP DOI BibTeX RDF	congestion prediction, rent rule, tangled logic, clustering
1	Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar	Physical design techniques for optimizing RTA-induced variations.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu	SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.	DATE	2010	DBLP BibTeX RDF
1	Yifang Liu, Yu Yang, Jiang Hu	Clustering-based simultaneous task and voltage scheduling for NoC systems.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Shiyan Hu, Jiang Hu	A fast general slew constrained minimum cost buffering algorithm.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
1	Shiyan Hu, Mahesh Ketkar, Jiang Hu	Gate Sizing for Cell-Library-Based Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Yang Liu, Tong Zhang, Jiang Hu	Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Rupak Samanta, Ganesh Venkataraman, Jiang Hu	Clock Buffer Polarity Assignment for Power Noise Reduction.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Pratik J. Shah, Jiang Hu	Impact of lithography-friendly circuit layout.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cd variation, lithography, wirelength, routing congestion
1	Yifang Liu, Jiang Hu	A new algorithm for simultaneous gate sizing and threshold voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	threshold voltage assignment, gate sizing
1	Yifang Liu, Jiang Hu	GPU-based parallelization for fast circuit optimization.	DAC	2009	DBLP DOI BibTeX RDF	VLSI circuit optimization, parallel computing, GPU
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Low Power Gated Clock Tree Driven Placement.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen	Power Grid Analysis and Optimization Using Algebraic Multigrid.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yifang Liu, Jiang Hu, Weiping Shi	Buffering Interconnect for Multicore Processor Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Robust Clock Tree Routing in the Presence of Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.	Integration	2008	DBLP DOI BibTeX RDF
1	Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.	ISQED	2008	DBLP DOI BibTeX RDF	clock mesh, dynamic time step rounding, simulation, macromodel
1	Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu	Elastic Timing Scheme for Energy-Efficient and Robust Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Elstic, Razor, Pipeline, Boosting
1	Yifang Liu, Jiang Hu, Weiping Shi	Multi-scenario buffer insertion in multi-core processor designs.	ISPD	2008	DBLP DOI BibTeX RDF	multi-core design, buffer insertion
1	Rupak Samanta, Jiang Hu, Peng Li	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
1	Sridhar Varadan, Janet Meiling Wang, Jiang Hu	Handling partial correlations in yield prediction.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker	Built-In Proactive Tuning System for Circuit Aging Resilience.	DFT	2008	DBLP DOI BibTeX RDF
1	Yifang Liu, Rupesh S. Shelar, Jiang Hu	Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
1	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze	Fast Algorithms for Slew-Constrained Minimum Cost Buffering.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Chin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path-Based Buffer Insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Bor-Yiing Su, Yao-Wen Chang, Jiang Hu	An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li	Utilizing Redundancy for Timing Critical Interconnect.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Jiang Hu, Frank Liu	Integrated Placement and Skew Optimization for Rotary Clocking.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi	An Efficient Algorithm for RLC Buffer Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
1	Yang Liu, Tong Zhang, Jiang Hu	Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Shiyan Hu, Jiang Hu	Pattern sensitive placement for manufacturability.	ISPD	2007	DBLP DOI BibTeX RDF	placement, physical design, manufacturability
1	Shiyan Hu, Mahesh Ketkar, Jiang Hu	Gate Sizing For Cell Library-Based Designs.	DAC	2007	DBLP DOI BibTeX RDF
1	Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Jiang Hu	A Placement Methodology for Robust Clocking.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Andi Winterboer, Jiang Hu, Johanna D. Moore, Clifford Nass	The influence of user tailoring and cognitive load on user performance in spoken dialogue systems.	INTERSPEECH	2007	DBLP BibTeX RDF
1	Jiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky	Context & usability testing: user-modeled information presentation in easy and difficult driving conditions.	CHI	2007	DBLP DOI BibTeX RDF	user modeling, usability testing, context of use, driving simulator, spoken dialogue system, information presentation
1	Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu	Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen	Modeling, optimization and control of rotary traveling-wave oscillator.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Shiyan Hu, Jiang Hu	Unified adaptivity optimization of clock and logic signals.	ICCAD	2007	DBLP DOI BibTeX RDF	clock signal tuning, logic signal tuning, post-silicon tuning, robustness, variation
1	Di Wu, Jiang Hu, Rabi N. Mahapatra	Antenna Avoidance in Layer Assignment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo	Analytical bound for unwanted clock skew due to wire width variation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via crosslinks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze	Accurate estimation of global buffer delay within a floorplan.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Zhuo Feng, Peng Li, Jiang Hu	Efficient Model Update for General Link-Insertion Networks.	ISQED	2006	DBLP DOI BibTeX RDF
1	Cheng Zhuo, Jiang Hu, Kangsheng Chen	An Improved AMG-based Method for Fast Power Grid Analysis.	ISQED	2006	DBLP DOI BibTeX RDF
1	Yang Liu, Tong Zhang, Jiang Hu	Low Power Trellis Decoder with Overscaled Supply Voltage.	SiPS	2006	DBLP DOI BibTeX RDF
1	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Statistical clock tree routing for robustness to process variations.	ISPD	2006	DBLP DOI BibTeX RDF	routing, robustness, process variations, clock tree
1	Bor-Yiing Su, Yao-Wen Chang, Jiang Hu	An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.	ISPD	2006	DBLP DOI BibTeX RDF	jumper insertion, antenna effect
1	Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li	Steiner network construction for timing critical nets.	DAC	2006	DBLP DOI BibTeX RDF	Steiner network, routing, redundancy, interconnect
1	Ke Cao, Sorin Dobre, Jiang Hu	Standard cell characterization considering lithography induced variations.	DAC	2006	DBLP DOI BibTeX RDF	process CD, CAD, OPC, design flow, standard cell, RET
1	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze	Fast algorithms for slew constrained minimum cost buffering.	DAC	2006	DBLP DOI BibTeX RDF	slew constraint, physical design, buffer insertion
1	Min-Seok Kim, Jiang Hu	Associative skew clock routing for difficult instances.	DATE	2006	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze	Integrated placement and skew optimization for rotary clocking.	DATE	2006	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu	High performance clock routing in X-architecture.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Mike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng	groupTime: preference based group scheduling.	CHI	2006	DBLP DOI BibTeX RDF	group calendaring, group scheduling, machine learning, supervised learning, intelligent user interfaces
1	Jamie Pearson, Jiang Hu, Holly P. Branigan, Martin J. Pickering, Clifford Nass	Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice.	CHI	2006	DBLP DOI BibTeX RDF	language behavior, HCI, adaptation, natural language, alignment, interaction technologies
1	Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen	Fast decap allocation based on algebraic multigrid.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi	A new RLC buffer insertion algorithm.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Rupak Samanta, Ganesh Venkataraman, Jiang Hu	Clock buffer polarity assignment for power noise reduction.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li	Combinatorial algorithms for fast clock mesh optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Navigating Register Placement for Low Power Clock Network Design.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Rishi Chaturvedi, Jiang Hu	An efficient merging scheme for prescribed skew clock routing.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Anand Rajaram, David Z. Pan, Jiang Hu	Improved algorithms for link-based non-tree clock networks for skew variability reduction.	ISPD	2005	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
1	Di Wu, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
1	Jiang Hu, Mike Brzozowski	Preference-Based Group Scheduling.	INTERACT	2005	DBLP DOI BibTeX RDF
1	QianYing Wang, Clifford Nass, Jiang Hu	Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences.	INTERACT	2005	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
1	Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path based buffer insertion.	DAC	2005	DBLP DOI BibTeX RDF	layout, physical design, global routing, buffer insertion, power minimization, interconnect synthesis
1	Ke Cao, Puneet Dhawan, Jiang Hu	Library cell layout with Alt-PSM compliance and composability.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu	Clock network minimization methodology based on incremental placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Making fast buffer insertion even faster via approximation techniques.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Register placement for low power clock network.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu	Skew scheduling and clock routing for improved tolerance to process variations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	layout embedding, skew scheduling, reliability, process variation, clock routing

Publications of "Jiang Hu" ( http://dblp.L3S.de/Authors/Jiang_Hu )