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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 16 occurrences of 12 keywords
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Results
Found 18 publication records. Showing 18 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su |
A Unitable Computing Architecture for Chip Multiprocessors.  |
Comput. J.  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Yu-Liang Chou |
A multi-streaming SIMD multimedia computing engine. |
Microprocessors and Microsystems - Embedded Hardware Design |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Ta-Li Yeh |
IRES: An integrated software and hardware interface framework for reconfigurable embedded system. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin |
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. |
J. Inf. Sci. Eng. |
2010 |
DBLP BibTeX RDF |
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| 1 | Jih-Ching Chiu, Kai-Ming Yang |
A Novel instruction stream buffer for VLIW architectures. |
Computers & Electrical Engineering |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen |
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. |
ICPP |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su |
A hyperscalar multi-core architecture. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors |
| 1 | Jih-Ching Chiu, Ta-Li Yeh, Mun-Kit Leong |
The Software and Hardware Integration Linker for Reconfigurable Embedded System. |
CSE |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng |
A multi-streaming SIMD architecture for multimedia applications. |
Conf. Computing Frontiers |
2009 |
DBLP DOI BibTeX RDF |
SIMD, streaming processing, streaming computing, processor-in-memory, mmx, multimedia extensions, pim |
| 1 | Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou |
Design of a novel SIMD architecture by fusing operations and registers. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
processor-in-memory, mmx, simd, multimedia extensions, pim |
| 1 | Jih-Ching Chiu, Kai-Ming Yang, Mu-Chi Chang |
The Rendezvous Mechanism for the Multi-core AMBA System. |
ICPP Workshops |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin |
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. |
J. Inf. Sci. Eng. |
2008 |
DBLP BibTeX RDF |
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| 1 | Jih-Ching Chiu, Ren-Bang Lin |
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung |
Variable-size data item placement for load and storage balancing. |
Journal of Systems and Software |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung |
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. |
J. Inf. Sci. Eng. |
2002 |
DBLP BibTeX RDF |
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| 1 | Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung |
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. |
J. Inf. Sci. Eng. |
2002 |
DBLP BibTeX RDF |
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| 1 | Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
Design of Instruction Stream Buffer with Trace Support for X86 Processors. (PDF / PS) |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache |
| 1 | Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung |
Instruction Cache Prefetching with Extended BTB. (PDF / PS) |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
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