Search results for "Jim D. Garside"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wei Song 0002, Doug Edwards, Jim D. Garside, William J. Bainbridge	Area efficient asynchronous SDM routers using 2-stage Clos switches.	DATE	2012	DBLP BibTeX RDF
1	Geoffrey Ndu, Jim D. Garside	Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration.	ARC	2012	DBLP DOI BibTeX RDF
1	Luis A. Plana, David M. Clark, Simon Davidson, Steve Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge	SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.	JETC	2011	DBLP DOI BibTeX RDF
1	Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods	The Amulet chips: Architectural development for asynchronous microprocessors.	ICECS	2009	DBLP DOI BibTeX RDF
1	Konstantinos Nikas, Matthew Horsnell, Jim D. Garside	An adaptive bloom filter cache partitioning scheme for multicore architectures.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	A. Robinson, Jim D. Garside	Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	processors, memory bandwidth, power efficiency, registers
1	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
1	C. Brej, Jim D. Garside	A Quasi-Delay-Insensitive Method to Overcome Transistor Variation.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	A CAM with mixed serial-parallel comparison for use in low energy caches.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury	An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Daranee Hormdee, Jim D. Garside, Stephen B. Furber	An asynchronous copy-back cache architecture.	Microprocessors and Microsystems	2003	DBLP DOI BibTeX RDF
1	Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu	SPA - a secure Amulet core for smartcard applications.	Microprocessors and Microsystems	2003	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Structures fo Speculation Control.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	An adaptive serial-parallel CAM architecture for low-power cache blocks.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low power, asynchronous circuits, low energy, CAM, cache design
1	Daranee Hormdee, Jim D. Garside, Stephen B. Furber	An Asynchronous Victim Cache.	DSD	2002	DBLP DOI BibTeX RDF	copy-back cache architecture, asynchronous design, victim cache
1	W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana	SPA - A Synthesisable Amulet Core for Smartcard pplications.	ASYNC	2002	DBLP BibTeX RDF
1	Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside	Logic Design of Asynchronous Circuits (Tutorial Abstract). (PDF / PS)	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Depth Control for Processor Power-Management.	ICCD	2002	DBLP DOI BibTeX RDF
1	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple	Power Management in the Amulet Microprocessors.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	David W. Lloyd, Jim D. Garside	A Practical Comparison of Asynchronous Design Styles.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Daranee Hormdee, Jim D. Garside	AMULET3i Cache Architecture.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli	AMULET3i - An Asynchronous System-on-Chip. (PDF / PS)	ASYNC	2000	DBLP DOI BibTeX RDF
1	Stephen B. Furber, David A. Edwards, Jim D. Garside	AMULET3: A 100 MIPS Asynchronous Embedded Processor. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	David W. Lloyd, Jim D. Garside, D. A. Gilbert	Memory Faults in Asynchronous Microprocessors.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Jim D. Garside, Stephen B. Furber, S.-H. Chung	AMULET3 Revealed.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
1	John V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple	AMULET1: A Asynchronous ARM Microprocessor.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF
1	D. A. Gilbert, Jim D. Garside	A Result Forwarding Mechanism for Asynchronous Pipelined Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	dependency, asynchronous, Exception, reorder buffer
1	Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver	AMULET2e: An Asynchronous Embedded Controller.	ASYNC	1997	DBLP DOI BibTeX RDF	Low power, Microprocessors, Asynchronous design, Embedded control
1	Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, John V. Woods	AMULET1: A Micropipelined ARM.	COMPCON	1994	DBLP BibTeX RDF
1	Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods	The Design and Evaluation of an Asynchronous Microprocessor.	ICCD	1994	DBLP BibTeX RDF
1	Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, John V. Woods	A micropipelined ARM.	VLSI	1993	DBLP BibTeX RDF
1	Jim D. Garside	A CMOS VLSI Implementation of an Asynchronous ALU.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
1	N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, John V. Woods	Register Locking in an Asynchronous Microprocessor.	ICCD	1992	DBLP BibTeX RDF

Publications of "Jim D. Garside" ( http://dblp.L3S.de/Authors/Jim_D._Garside )