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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 5 occurrences of 5 keywords
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Results
Found 11 publication records. Showing 11 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie |
Three-dimensional Integrated Circuits: Design, EDA, and Architecture.  |
Foundations and Trends in Electronic Design Automation  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jin Ouyang, Yuan Xie |
Enabling quality-of-service in nanophotonic network-on-chip. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie |
A frequent-value based PRAM memory architecture. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu |
F2BFLY: an on-chip free-space optical network with wavelength-switching. |
ICS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jin Ouyang, Yuan Xie |
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. |
MICRO |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie |
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller |
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC |
| 1 | Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin |
Arithmetic unit design using 180nm TSV-based 3D stacking technology. |
3DIC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie |
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). |
3DIC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Yibo Chen, Jin Ouyang, Yuan Xie |
ILP-based scheme for timing variation-aware scheduling and resource binding. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Jin Ouyang, Yuan Xie |
Power optimization for FinFET-based circuits using genetic algorithms. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #11 of 11 (100 per page; Change: )
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