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Found 8 publication records. Showing 8 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu |
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
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| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low Power Pulse Generator Design Using Hybrid Logic. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
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| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
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| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low Complexity Dual-Mode Pulse Generator Designs. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multipliers Using Enhenced Row Bypassing Schemes. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
A high speed and energy efficient full adder design using complementary & level restoring carry logic. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
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