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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 43 occurrences of 26 keywords
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Results
Found 66 publication records. Showing 66 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng |
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li |
On test and repair of 3D random access memory. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng |
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Jin-Fu Li |
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Jin-Fu Li |
SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories. |
J. Inf. Sci. Eng. |
2011 |
DBLP BibTeX RDF |
|
| 1 | Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li |
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu |
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu |
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li |
Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou |
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou |
A Built-in Method to Repair SoC RAMs in Parallel. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou |
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
test, test scheduling, repair, RAM, built-in self-repair |
| 1 | Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
A Test Integration Methodology for 3D Integrated Circuits. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li |
A low-cost built-in self-test scheme for an array of memories. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li |
A low-cost and scalable test architecture for multi-core chips. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Cheng-Wen Wu |
Is 3D integration an opportunity or just a hype? |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li |
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Yun-Chao You, Jin-Fu Li |
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. |
SoCC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li |
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks. |
IEEE Micro |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bing-Wei Huang, Jin-Fu Li |
Efficient diagnosis algorithms for drowsy SRAMs. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Jin-Fu Li |
Testability Exploration of 3-D RAMs and CAMs. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li |
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsing-Chen Lu, Jin-Fu Li |
A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong-Ming Shieh, Jin-Fu Li |
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang |
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC) |
| 1 | Tsu-Wei Tseng, Jin-Fu Li |
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Chao-Da Huang |
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li |
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li |
Transparent-Test Methodologies for Random Access Memories Without/With ECC. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey |
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Yu-Jen Huang, Jin-Fu Li |
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults. |
IET Computers & Digital Techniques |
2007 |
DBLP BibTeX RDF |
|
| 1 | Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng |
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
Raisin: Redundancy Analysis Algorithm Simulation. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
repair rate, BIRA, Raisin, yield, BISR, redundancy analysis, algorithm simulation |
| 1 | Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen |
A Built-In Self-Repair Scheme for Multiport RAMs. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey |
Design of cost-efficient memory-based FFT processors using single-port memories. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng |
Diagnosing scan chains using SAT-based diagnostic pattern generation. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen |
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Jin-Fu Li |
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. |
European Test Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang |
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li |
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu |
A built-in self-repair design for RAMs with 2-D redundancy. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li |
Testing priority address encoder faults of content addressable memories. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li |
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Chou-Kun Lin |
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey |
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang |
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li |
Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults. |
IEICE Transactions |
2004 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fu Li, Chih-Chiang Hsu |
Efficient Test Methodologies for Conditional Sum Adders. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Chao-Da Huang |
An Efficient Diagnosis Scheme for Random Access Memories. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu |
Built-in redundancy analysis for memory yield improvement. |
IEEE Transactions on Reliability |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
march test algorithm, memory diagnostics, BIST, memory testing, CAM |
| 1 | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair |
| 1 | Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li |
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. |
MTDT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin |
A Hierarchical Test Methodology for Systems on Chip. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Cheng-Wen Wu |
Efficient FFT network testing and diagnosis schemes. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin |
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory |
| 1 | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test |
| 1 | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosing Embedded Content Addressable Memories. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin |
A Hierarchical Test Scheme for System-On-Chip Designs. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
simulation, memory testing, embedded memory, redundancy analysis, memory repair |
| 1 | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
simulation, memory testing, embedded memory, redundancy analysis, memory repair |
| 1 | Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
March-based RAM diagnosis algorithms for stuck-at and coupling faults. |
ITC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Cheng-Wen Wu |
Memory fault diagnosis by syndrome compression. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin |
A built-in self-test and self-diagnosis scheme for embedded SRAM. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM |
| 1 | Jin-Fu Li, Cheng-Wen Wu |
Testable and Fault Tolerant Design for FFT Networks. (PDF / PS) |
DFT |
1999 |
DBLP DOI BibTeX RDF |
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