Search results for "Jinian Bian"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian	PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto	Buffer Planning for IP Placement Using Sliced-LFF.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian	Processor Accelerator Customization through Data Flow Graph Exploration.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai	A fast recursive detailed routing algorithm for hierarchical FPGAs.	CSCWD	2011	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian	Instruction-level hardware/software partition through DFG exploration.	CSCWD	2011	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian	Pruning-based trace signal selection algorithm.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Hui Dai, Qiang Zhou, Jinian Bian	Multilevel Optimization for Large-Scale Hierarchical FPGA Placement.	J. Comput. Sci. Technol.	2010	DBLP DOI BibTeX RDF
1	Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian	A low power clock network placement framework.	ISQED	2010	DBLP DOI BibTeX RDF
1	Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong	Mutation-based diagnostic test generation for hardware design error diagnosis.	ITC	2010	DBLP DOI BibTeX RDF
1	Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian	An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.	CSCWD	2010	DBLP DOI BibTeX RDF
1	Wentao Sui, Sheqin Dong, Jinian Bian	Wirelength-driven force-directed 3D FPGA placement.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	SA, partition, placement, legalization, 3-D, force-directed
1	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	Bus via reduction based on floorplan revising.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	floorplan revising, via reduction, bus routing
1	Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao (eds.)	Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China	FPT	2010	DBLP BibTeX RDF
1	Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian	Behavioral level dual-vth design for reduced leakage power with thermal awareness.	DATE	2010	DBLP BibTeX RDF
1	Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian	Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong, Kang Zhao	Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto	Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong	Cell shifting aware of wirelength and overlap.	ISQED	2009	DBLP DOI BibTeX RDF
1	Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong	Random stimulus generation with self-tuning.	CSCWD	2009	DBLP DOI BibTeX RDF
1	Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao	Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Junbo Yu, Qiang Zhou, Jinian Bian	Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Dawei Liu, Qiang Zhou, Jinian Bian, Yanming Jia	Global density smoothing technique for analytical placement algorithm.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
1	Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong	Fast placement for large-scale hierarchical FPGAs.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
1	Lixin Cheng, Jinian Bian, Yunyun Liu	An approach to synthesis delay semantics in VHDL.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto	Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto	Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Kun Tong, Jinian Bian, Haili Wang	A cooperative universal data model platform for the data-centric electronic system-level design.	Advanced Engineering Informatics	2008	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto	Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration.	ISQED	2008	DBLP DOI BibTeX RDF
1	Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.	FPL	2008	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto	Cache miss reduction through hardware-assisted loop optimization.	CSCWD	2008	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto	HyMacs: hybrid memory access optimization based on custom-instruction scheduling.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asip, cad algorithm, hardware/software co-design
1	Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	A novel fixed-outline floorplanner with zero deadspace for hierarchical design.	ICCAD	2008	DBLP DOI BibTeX RDF	floorplanner, soft modules, zero deadspace, fixed-outline
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai	Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong	A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design.	CSCWD	2007	DBLP DOI BibTeX RDF
1	Hui Zhang, Jinian Bian	A Management System of Metropolis Energy Information.	CSCWD	2007	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong	An effective buffer planning algorithm for IP based fixed-outline SOC placement.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline
1	Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao	EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure.	DAC	2007	DBLP DOI BibTeX RDF
1	Yanhua Wang, Qiang Zhou, Jinian Bian, Junhua Qu	VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Chenqian Jiang, Jinian Bian, Kang Zhao	Power-driven Real-time System Design with Energy Efficiency via ISA Customization.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani	Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	floorplanning, thermal, 3D IC
1	Ming Zhu, Jinian Bian, Weimin Wu	A novel collaborative scheme of simulation and model checking for system properties verification.	Computers in Industry	2006	DBLP DOI BibTeX RDF
1	Shujun Deng, Weimin Wu, Jinian Bian	Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving.	CSCWD (Selected Papers)	2006	DBLP DOI BibTeX RDF
1	Kun Tong, Jinian Bian, Haili Wang	Universal data model platform: the data-centric evolution for system level codesign.	CSCWD	2006	DBLP DOI BibTeX RDF
1	Shujun Deng, Weimin Wu, Jinian Bian	Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving.	CSCWD	2006	DBLP DOI BibTeX RDF
1	Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu	AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design.	CSCWD	2006	DBLP DOI BibTeX RDF
1	Yawen Niu, Jinian Bian, Haili Wang, Kun Tong	An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design.	CSCWD (Selected Papers)	2006	DBLP DOI BibTeX RDF
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Integrating dynamic thermal via planning with 3D floorplanning algorithm.	ISPD	2006	DBLP DOI BibTeX RDF	3D floorplanning, thermal optimization, thermal via
1	Zhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao	High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian	A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Liang Zhu, Jinian Bian	From Software to Hardware - A Novel TLM Auto-Generating Method.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Kang Zhao, Jinian Bian, Sheqin Dong	A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization.	JCIS	2006	DBLP DOI BibTeX RDF
1	Haili Wang, Jinian Bian, Qiang Wu, Yunfeng Wang	iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration.	CSCWD	2005	DBLP DOI BibTeX RDF
1	Jianzhou Zhao, Jinian Bian, Weimin Wu	Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs.	CSCWD	2005	DBLP DOI BibTeX RDF
1	Feng Lin, Haili Wang, Jinian Bian	HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design.	FPT	2005	DBLP BibTeX RDF
1	Qiang Wu, Jinian Bian, Hongxi Xue	System-level architectural exploration using allocation-on-demand technique.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yunfeng Wang, Jinian Bian, Xianlong Hong	Interconnect delay optimization via high level re-synthesis after floorplanning.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu	A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.	ICESS	2005	DBLP DOI BibTeX RDF
1	Jianzhou Zhao, Jinian Bian, Weimin Wu	PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie.	COMPSAC	2004	DBLP DOI BibTeX RDF
1	Haili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang	CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems.	ICESS	2004	DBLP DOI BibTeX RDF
1	Ming Zhu, Jinian Bian, Weimin Wu	Model Optimization Techniques in a Verification Platform for Classified Properties.	ICESS	2004	DBLP DOI BibTeX RDF
1	Qiang Wu, Jinian Bian, Hongxi Xue	A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design.	ICESS	2004	DBLP DOI BibTeX RDF
1	Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue	Property Classification for Functional Verification Based.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Wangning Long, Yu-Liang Wu, Jinian Bian	IBAW: an implication-tree based alternative-wiring logic transformation algorithm.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong	FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.	ASP-DAC	1999	DBLP DOI BibTeX RDF	Finite State Machine, VHDL, Symbolic Model Checking

Publications of "Jinian Bian" ( http://dblp.L3S.de/Authors/Jinian_Bian )