Search results for "Jinn-Shyan Wang"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin	Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang	A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh	Design of High-Performance CMOS Level Converters Considering PVT Variations.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng	A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh	Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang	A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang	A 55nm 1GHz one-cycle-locking de-skewing circuit.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang	VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism.	IEEE Trans. Circuits Syst. Video Techn.	2009	DBLP DOI BibTeX RDF
1	Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo	A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications.	IEEE Trans. Circuits Syst. Video Techn.	2009	DBLP DOI BibTeX RDF
1	Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang	No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.	DAC	2009	DBLP DOI BibTeX RDF	level-1 non-uniform cache architecture, ring interconnection, single-cycle transactions, multi-core, NOC, SOC, arbitration, memory structure
1	Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang	A dynamic quality-scalable H.264 video encoder chip.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo	A Dynamic Quality-scalable H.264 Video Encoder.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Tzu-Yuan Kuo, Jinn-Shyan Wang	A low-voltage latch-adder based tree multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo	A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.	SiPS	2007	DBLP DOI BibTeX RDF
1	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang	A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264.	IEEE Trans. Circuits Syst. Video Techn.	2006	DBLP DOI BibTeX RDF
1	Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang	A Condition-based Intra Prediction Algorithm for H.264/AVC.	ICME	2006	DBLP DOI BibTeX RDF
1	Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang	A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang	An 830mW, 586kbps 1024-bit RSA chip design.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu	An improved SAR controller for DLL applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo	A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu	Design of STR level converters for SoCs using the multi-island dual-VDD design technique.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen	An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.	IEEE Trans. Circuits Syst. Video Techn.	2005	DBLP DOI BibTeX RDF
1	Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo	An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.	ISLPED	2005	DBLP DOI BibTeX RDF	MPEG-4/AVC, direct 2-D integer transform, low-power design, H.264, HDTV, digital cinema
1	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang	An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang	An all-digital pulsewidth control loop.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh	A low-power high-SFDR CMOS direct digital frequency synthesizer.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang	Low-power fixed-width array multipliers.	ISLPED	2004	DBLP DOI BibTeX RDF	fixed-width multiplier, left-to-right multiplier, reduced-width multiplier, low power
1	Yi-Ming Wang, Jinn-Shyan Wang	A reliable low-power fast skew-compensation circuit.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh	A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.	ICME	2004	DBLP BibTeX RDF
1	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen	A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.	ISCAS	2004	DBLP BibTeX RDF
1	Yi-Ming Wang, Jinn-Shyan Wang	An all-digital 50% duty-cycle corrector.	ISCAS	2004	DBLP BibTeX RDF
1	Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh	Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs.	ISCAS	2004	DBLP BibTeX RDF
1	Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen	Design theory and implementation for low-power segmented bus systems.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
1	Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang	Energy Efficient Caching-on-Cache Architectures for Embedded Systems.	J. Inf. Sci. Eng.	2003	DBLP BibTeX RDF
1	Yuan-Pao Hsu, Kao-Shing Hwang, Jinn-Shyan Wang	An Associative Architecture of CMAC for Mobile Robot Motion Control.	J. Inf. Sci. Eng.	2002	DBLP BibTeX RDF
1	Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang	Charge-sharing alleviation and detection for CMOS domino circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang	A high-speed CMOS incrementer/decrementer.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Sheng-Yeh Lai, Jinn-Shyan Wang	A high-efficiency CMOS charge pump circuit.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
1	Jinn-Shyan Wang, Po-Hui Yang	Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang	A new CMAC neural network architecture and its ASIC realization.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone	Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang	Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.	ICCAD	2000	DBLP BibTeX RDF
1	J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen	Segmented bus design for low-power systems.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang	Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs.	DAC	1999	DBLP DOI BibTeX RDF
1	Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang	Technnology Mapping for Low Power.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Ching-Rong Chang, Jinn-Shyan Wang	A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang	A cell selection strategy for low power applications.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone	Charge Sharing Fault Detection for CMOS Domino Logic Circuits. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
1	Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng	Low-power embedded SRAM macros with current-mode read/write operations.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu	Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.	ISCAS	1995	DBLP BibTeX RDF

Publications of "Jinn-Shyan Wang" ( http://dblp.L3S.de/Authors/Jinn-Shyan_Wang )