| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
A low-power management technique for high-performance domino circuits.  |
ASP-DAC  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng |
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ke Xu, Tsu-Ming Liu, Jiun-In Guo, Oliver Chiu-sing Choy |
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding. |
Signal Processing Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
Dynamic voltage domain assignment technique for low power performance manageable cell based design. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kheng-Joo Tan, Jia-Wei Gong, Bing-Tsung Wu, Dou-Cheng Chang, Hsin-Yi Li, Yi-Mao Hsiao, Yung-Chung Chen, Shi-Wu Lo, Yuan-Sun Chu, Jiun-In Guo |
A remote thin client system for real time multimedia streaming over VNC. |
ICME |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Chuan Yang, Kheng-Joo Tan, Yao-Chang Yang, Jiun-In Guo |
Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC. |
ICME |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang-Hung Tsai, Kheng-Joo Tan, Ching-Lung Su, Jiun-In Guo |
A group of macroblock based motion estimation algorithm supporting adaptive search range for H.264 video coding. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
H.264, MPEG, Video decoder |
| 1 | Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang |
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. |
IEEE Trans. Circuits Syst. Video Techn. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yao-Chang Yang, Jiun-In Guo |
High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV Applications. |
IEEE Trans. Circuits Syst. Video Techn. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo |
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. |
IEEE Trans. Circuits Syst. Video Techn. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Guo-An Jian, Ting-Yu Huang, Jui-Chin Chu, Jiun-In Guo |
Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors. |
ITNG |
2009 |
DBLP DOI BibTeX RDF |
software optimization |
| 1 | Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang |
A dynamic quality-scalable H.264 video encoder chip. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo |
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo |
A Dynamic Quality-scalable H.264 Video Encoder. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo |
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
A Multi-standard Video Decoder for High Definition Video Applications. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Guo-An Jian, Jui-Chin Chu, Ting-Yu Huang, Tao-Cheng Chang, Jiun-In Guo |
A System Architecture Exploration on the Configurable HW/SW Co-design for H.264 Video Decoder. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao-Cheng Chang, Hung-Wei Shen, Jiun-In Guo |
A Low Complexity Error Concealment Method for H.264 Video Coding Facilitating Hardware Realization. |
ISPAN |
2009 |
DBLP DOI BibTeX RDF |
H.264, Error concealment |
| 1 | Guo-An Jian, Jui-Chin Chu, Jiun-In Guo |
Optimization of AVS-M Video Decoder for Real-time Implementation on Embedded RISC Processors. |
IIH-MSP |
2009 |
DBLP DOI BibTeX RDF |
software optimization |
| 1 | Ting-Yu Huang, Guo-An Jian, Jui-Chin Chu, Ching-Lung Su, Jiun-In Guo |
Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ping-Tsung Wu, Tzu-Chun Chang, Ching-Lung Su, Jiun-In Guo |
A H.264 basic-unit level rate control algorithm facilitating hardware realization. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo |
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo |
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Guo-An Jian, Jiun-In Guo |
Low Complexity Multi-Standard Video Player for Portable Multimedia Applications. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo |
A Low Latency Memory Controller for Video Coding Systems. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo |
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Guo-An Jian, Chih-Da Chien, Jiun-In Guo |
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang |
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. |
IEEE Trans. Circuits Syst. Video Techn. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng |
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Shuan Lee, Jui-Chin Chu, Jiun-In Guo |
Predictive Mode Searching Policy for H.264/AVC Intra Prediction. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao Li, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng |
Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo |
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. |
ICME |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, Jiun-In Guo |
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. |
ICME |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang |
A Condition-based Intra Prediction Algorithm for H.264/AVC. |
ICME |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo |
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen |
Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo |
Low-power mechanism with power block management. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo |
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen |
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen |
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. |
IEEE Trans. Circuits Syst. Video Techn. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen |
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. |
IEEE Trans. Circuits Syst. Video Techn. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo |
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
MPEG-4/AVC, direct 2-D integer transform, low-power design, H.264, HDTV, digital cinema |
| 1 | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang |
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo |
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo |
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Rei-Chin Ju, Jia-Wei Chen |
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization. |
IEEE Trans. Circuits Syst. Video Techn. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo |
A high-performance MPEG4 bitstream processing core. |
ICME |
2004 |
DBLP BibTeX RDF |
|
| 1 | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh |
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. |
ICME |
2004 |
DBLP BibTeX RDF |
|
| 1 | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen |
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen |
A power-aware IP core generator for the one-dimensional discrete Fourier transform. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen |
A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Hun-Chen Chen, Jiun-In Guo, Lin-Chieh Huang, Jui-Cheng Yen |
Design and Realization of a New Signal Security System for Multimedia Data Transmission. |
EURASIP J. Adv. Sig. Proc. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Jui-Cheng Yen |
An Efficient IDCT Processor Design for HDTV Applications. |
VLSI Signal Processing |
2003 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution |
| 1 | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
A memory efficient realization of cyclic convolution and its application to discrete cosine transform. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen |
A new 2-D 8/spl times/8 DCT/IDT core design using group distributed arithmetic. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin |
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien |
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. |
Journal of Circuits, Systems, and Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Hun-Chen Chen, Jui-Cheng Yen, Jiun-In Guo |
Design of a New Cryptography System. |
IEEE Pacific Rim Conference on Multimedia |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jui-Cheng Yen, Jiun-In Guo |
Design of a new signal security system. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
A new group distributed arithmetic design for the one dimensional discrete Fourier transform. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Chien-Chang Lin |
A new hardware efficient design for the one dimensional discrete Fourier transform. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Chih-Chen Li |
A generalized architecture for the one-dimensional discrete cosine and sine transforms. |
IEEE Trans. Circuits Syst. Video Techn. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo |
A new DA-based array for one dimensional discrete Hartley transform. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo |
A low cost 2-D inverse discrete cosine transform design for image compression. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo |
An efficient design for one-dimensional discrete Hartley transform using parallel additions. |
IEEE Transactions on Signal Processing |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jui-Cheng Yen, Jiun-In Guo, Hun-Chen Chen |
A new k-winners-take-all neural network and its array architecture. |
IEEE Transactions on Neural Networks |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
A New Array Architecture for Prime-Length Discrete Cosine Transform. |
IEEE Transactions on Signal Processing |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen |
A Multi-phase Shared Bus Structure for the Fast Fourier Transform. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
| 1 | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
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