Search results for "Joan Figueras"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Elena I. Vatajelu, Joan Figueras	Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation.	DATE	2012	DBLP BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Gate Leakage Impact on Full Open Defects in Interconnect Lines.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Elena I. Vatajelu, Alvaro Gómez-Pau, Michel Renovell, Joan Figueras	Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Elena I. Vatajelu, Joan Figueras	Robustness analysis of 6T SRAMs in memory retention mode under PVT variations.	DATE	2011	DBLP DOI BibTeX RDF
1	Elena Ioana Vatajel, Joan Figueras	Statistical analysis of 6T SRAM data retention voltage under process variation.	DDECS	2011	DBLP DOI BibTeX RDF
1	Nivard Aymerich, A. Asenov, A. Brown, Ramon Canal, B. Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, P. Pouyan, Tanausu Ramirez, Antonio Rubio, I. Vatajelu, Xavier Vera, X. Wang, Paul Zuber	New reliability mechanisms in memory design for sub-22nm technologies.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Neagu Madalin, Liviu Miclea, Joan Figueras	Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Víctor H. Champac, Victor Avendaño, Joan Figueras	Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras	Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Diagnosis of full open defects in interconnect lines with fan-out.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	A. Gomez, R. Sanahuja, L. Balado, Joan Figueras	Analog circuit test based on a digital signature.	DATE	2010	DBLP BibTeX RDF
1	Luz Balado, Emili Lupon, Joan Figueras, Miquel Roca, Eugeni Isern, Rodrigo Picos	Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras	Delay caused by resistive opens in interconnecting lines.	Integration	2009	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras	Experimental Characterization of CMOS Interconnect Open Defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Time-dependent Behaviour of Full Open Defects in Interconnect Lines.	ITC	2008	DBLP DOI BibTeX RDF
1	Francesc Moll, Joan Figueras, Antonio Rubio	Data Dependence of Delay Distribution for a Planar Bus.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Full Open Defects in Nanometric CMOS.	VTS	2008	DBLP DOI BibTeX RDF	interconnect open, gate leakage current, CMOS
1	Salvador Manich, L. Garcia-Deiros, Joan Figueras	Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi	Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.	VTS	2007	DBLP DOI BibTeX RDF	Current Based Diagnosis, Current Signatures, I_DDQ, Very Low Voltage, CMOS, Bridging Defect
1	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi	Diagnosis of Full Open Defects in Interconnecting Lines.	VTS	2007	DBLP DOI BibTeX RDF	Defect Diagnosis, Full Open Defect, Interconnecting Line, CMOS
1	L. Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras	Lissajous Based Mixed-Signal Testing for N-Observable Signals.	DDECS	2006	DBLP BibTeX RDF
1	R. Sanahuja, V. Barcons, L. Balado, Joan Figueras	Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	X-Y zoning, Lissajous curves, BIST, parametric testing
1	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras	On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	low-power, BIST, RTL, test quality, defects-based test
1	Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	Analog Switch, DC defective behaviour, DC test, open defect, bridging defect
1	Salvador Manich, L. García, L. Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras	BIST Technique by Equally Spaced Test Vector Sequences.	VTS	2004	DBLP DOI BibTeX RDF
1	Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden	Test Engineering Education in Europe: the EuNICE-Test Project.	MSE	2003	DBLP DOI BibTeX RDF
1	Antoni Ferré, Joan Figueras	Leakage power bounds in CMOS digital technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.	ITC	2002	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	FPGA, test, ATPG
1	Paolo Prinetto, Joan Figueras	Guest Editorial.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF
1	Antoni Ferré, Joan Figueras	LEAP: An Accurate Defect-Free IDDQ Estimator.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	leakage current, I DDQ
1	Antonio Zenteno, Víctor H. Champac, Joan Figueras	Detectability Conditions of Full Opens in the Interconnections.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	logic testing, IDDQ testing, opens, defect modeling
1	Anna Maria Brosa, Joan Figueras	Digital Signature Proposal for Mixed-Signal Circuits.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	BIST, analog test, mixed-signal test
1	Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian	IS-FPGA : a new symmetric FPGA architecture with implicit scan.	ITC	2001	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	Testing the Local Interconnect Resources of SRAM-Based FPGA's.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	FPGA, VLSI, test, ATPG
1	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos	Low Power BIST by Filtering Non-Detecting Vectors.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	low power BIST, low energy consumption, LFSR, gated clock
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	FPGA, test, ATPG, iterative testing
1	Anna Maria Brosa, Joan Figueras	On Maximizing the Coverage of Catastrophic and Parametric Faults.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	analog & mixed-signal testing, fault coverage, set covering problems
1	Anna Maria Brosa, Joan Figueras	Digital signature proposal for mixed-signal circuits.	ITC	2000	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
1	Anna Maria Brosa, Joan Figueras	Characterization of Floating Gate Defects in Analog Cells.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	floating gate defect, low-power/low-voltage analog circuits, analog testing
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	FPGA, test, ATPG, RAM, iterative testing
1	Víctor H. Champac, José Castillejos, Joan Figueras	IDDQ Testing of Opens in CMOS SRAMs.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	data retention faults, memory testing, opens, IDDQ
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	Minimizing the Number of Test Configurations for Different FPGA Families.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	FPGA, ATPG
1	Anna Maria Brosa, Joan Figueras	On Optimizing Test Strategies for Analog Cells.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.	DATE	1999	DBLP DOI BibTeX RDF
1	Josep Rius, Joan Figueras	Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.	DATE	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	Testing the Interconnect of RAM-Based FPGAs.	IEEE Design & Test of Computers	1998	DBLP DOI BibTeX RDF
1	Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras	IDDQ testing: state of the art and future trends.	Integration	1998	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	SRAM-based FPGA's: testing the LUT/RAM modules.	ITC	1998	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.	FPL	1998	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Víctor H. Champac, José Castillejos, Joan Figueras	IDDQ Testing of Opens in CMOS SRAMs. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi	Novel Technique for Testing FPGAs.	DATE	1998	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, testing, reuse, diagnosis
1	Rosa Rodríguez-Montañés, Joan Figueras	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ testability, CMOS, deep-submicron
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	RAM-Based FPGA's: A Test Approach for the Configurable Logic.	DATE	1998	DBLP DOI BibTeX RDF
1	Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras	Fault-Secure Parity Prediction Arithmetic Operators.	IEEE Design & Test of Computers	1997	DBLP DOI BibTeX RDF
1	Antoni Ferré, Joan Figueras	IDDQ Characterization in Submicron CMOS.	ITC	1997	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	FPGA, VLSI, Test, CMOS, IC
1	Rosa Rodríguez-Montañés, Joan Figueras	Bridges in sequential CMOS circuits: current-voltage signatur.	VTS	1997	DBLP DOI BibTeX RDF	sequential CMOS circuits, current-voltage signature, I/sub DDQ/-V/sub DD/ signature, control loop nodes, fault diagnosis, fault diagnosis, temperature dependence, bridging defects
1	Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian	Power Dissipation During Testing: Should We Worry About it? (PDF / PS)	VTS	1997	DBLP DOI BibTeX RDF
1	Michel Renovell, Joan Figueras, Yervant Zorian	Test of RAM-based FPGA: methodology and application to the interconnect.	VTS	1997	DBLP DOI BibTeX RDF	RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect
1	Salvador Manich, Joan Figueras	Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras	Bridging defects resistance in the metal layer of a CMOS process.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	resistance of the bridge, defect modelling, bridging defects, CMOS process
1	Josep Rius, Joan Figueras	Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	I DDQ testability, Built-in Current Sensors, current testing
1	Antoni Ferré, Joan Figueras	On estimating bounds of the quiescent current for I/sub DDQ/ testin.	VTS	1996	DBLP DOI BibTeX RDF	quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach
1	Salvador Manich, Michael Nicolaidis, Joan Figueras	Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring.	VTS	1996	DBLP DOI BibTeX RDF	mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
1	Joan Figueras, Michel Renovell	Current testing in dynamic CMOS circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	dynamic CMOS, test technique, integrated circuit, Current testing
1	Eugeni Isern, Joan Figueras	IDDQ Test and Diagnosis of CMOS Circuits.	IEEE Design & Test of Computers	1995	DBLP DOI BibTeX RDF
1	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
1	Josep Rius, Joan Figueras	Detecting I/sub DDQ/ defective CMOS circuits by depowering.	VTS	1995	DBLP DOI BibTeX RDF	I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance
1	Víctor H. Champac, Antonio Rubio, Joan Figueras	Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, Joan Figueras	Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	Eugeni Isern, Joan Figueras	Test of Bridging Faults in Scan-based Sequential Circuits.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	Eugeni Isern, Joan Figueras	Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits.	ITC	1993	DBLP DOI BibTeX RDF
1	Michel Renovell, Joan Figueras	Current Testing Viability in Dynamic CMOS Circuits.	DFT	1993	DBLP BibTeX RDF
1	Víctor H. Champac, Antonio Rubio, Joan Figueras	Analysis of the Floating Gate Defect in CMOS.	DFT	1993	DBLP BibTeX RDF
1	Josep Rius, Joan Figueras	Proportional BIC sensor for current testing.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	Built-in integrated sensor, CMOS lateral BJT, gate controlled BJT, I DDQ measure, current test
1	J. A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio	Quiescent current analysis and experimentation of defective CMOS circuits.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	Bridging failures, floating gate opens, intentionally designed defective circuits defects, current testing, defect modeling, gate oxide shorts
1	Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls	Bridging Defects Resistance Measurements in a CMOS Process.	ITC	1992	DBLP DOI BibTeX RDF
1	Juan A. Carrasco, Joan Figueras, Annie Kuntzmann-Combelles	Evaluation of safety-oriented two-version architectures.	Journal of Systems and Software	1991	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, J. A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio	Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.	ITC	1991	DBLP DOI BibTeX RDF

Publications of "Joan Figueras" ( http://dblp.L3S.de/Authors/Joan_Figueras )