Search results for "Joel Coburn"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Adrian M. Caulfield, Todor I. Mollov, Louis Alex Eisner, Arup De, Joel Coburn, Steven Swanson	Providing safe, user space access to fast, solid state disks.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Devi Yalamarthy, Joel Coburn, Rajesh Gupta, Glen Edwards, Mark Kelly	Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Joel Coburn, Adrian M. Caulfield, Ameen Akel, Laura M. Grupp, Rajesh K. Gupta, Ranjit Jhala, Steven Swanson	NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories.	ASPLOS	2011	DBLP DOI BibTeX RDF
1	Adrian M. Caulfield, Joel Coburn, Todor I. Mollov, Arup De, Ameen Akel, Jiahua He, Arun Jagatheesan, Rajesh K. Gupta, Allan Snavely, Steven Swanson	Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing.	SC	2010	DBLP DOI BibTeX RDF
1	Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson	Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1	Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, Jack K. Wolf	Characterizing flash memory: anomalies, observations, and applications.	MICRO	2009	DBLP DOI BibTeX RDF	flash memory, characterization, non-volatile
1	Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Mendel Rosenblum	Streamware: programming general-purpose multicore processors using streams.	ASPLOS	2008	DBLP DOI BibTeX RDF	general-purpose multicore processors, programming, streams, runtime system
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Hardware Accelerated Power Estimation	CoRR	2007	DBLP BibTeX RDF
1	Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally	Architectural Support for the Stream Execution Model on General-Purpose Processors.	PACT	2007	DBLP DOI BibTeX RDF
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar	SECA: security-enhanced communication architecture.	CASES	2005	DBLP DOI BibTeX RDF	AMBA Bus, security-aware design, small embedded systems, security, communication, access control, architecture, intrusion detection, system-on-chip (SoC), attacks, bus, digital rights management (DRM)
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Hardware Accelerated Power Estimation.	DATE	2005	DBLP DOI BibTeX RDF

Publications of "Joel Coburn" ( http://dblp.L3S.de/Authors/Joel_Coburn )