| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kenneth M. Zick, John P. Hayes |
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems.  |
TRETS  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandru Paler, Ilia Polian, John P. Hayes |
Detection and diagnosis of faulty quantum circuits. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker |
Modeling and Mitigating Transient Errors in Logic Circuits. |
IEEE Trans. Dependable Sec. Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, John P. Hayes |
Selective Hardening: Toward Cost-Effective Error Tolerance. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes |
Tomographic Testing and Validation of Probabilistic Circuits. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
Probabilistic testing, quantum computing |
| 1 | Chien-Chih Yu, John P. Hayes |
Trigonometric method to handle realistic error probabilities in logic circuits. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dae Young Lee, David D. Wentzloff, John P. Hayes |
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth M. Zick, John P. Hayes |
Toward Physically-Adaptive Computing. |
SASO |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth M. Zick, John P. Hayes |
Self-Test and Adaptation for Random Variations in Reliability. |
FPL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, John P. Hayes |
Advanced modeling of faults in Reversible circuits. |
EWDTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Chih Yu, John P. Hayes |
Scalable and accurate estimation of probabilistic behavior in sequential circuits. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth M. Zick, John P. Hayes |
On-line sensing for healthier FPGA systems. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management |
| 1 | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes |
Signature-Based SER Analysis and Design of Logic Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | George F. Viamontes, Igor L. Markov, John P. Hayes |
Quantum Circuit Simulation. |
|
2009 |
DOI RDF |
|
| 1 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
Improving testability and soft-error resilience through retiming. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
testability, soft errors, retiming |
| 1 | Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol |
Contactless testing: Possibility or pipe-dream? |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kenneth M. Zick, John P. Hayes |
On-line characterization and reconfiguration for single event upset variations. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes |
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
fault tolerance, Symbolic analysis |
| 1 | Ketan N. Patel, Igor L. Markov, John P. Hayes |
Optimal synthesis of linear reversible circuits. |
Quantum Information & Computation |
2008 |
DBLP BibTeX RDF |
|
| 1 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
On the role of timing masking in reliable logic circuit design. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
timing, soft errors, SEUs |
| 1 | Sungsoon Cho, John P. Hayes |
Optimizing router locations for minimum-energy wireless networks. |
LCN |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
Tracking Uncertainty with Probabilistic Logic Circuit Testing. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
probabilistic faults, logic circuit testing, fault-modeling framework, test-vector sensitivity, integer linear programming |
| 1 | Sungsoon Cho, John P. Hayes |
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks. |
LCN |
2007 |
DBLP DOI BibTeX RDF |
MANET, energy efficiency, power control, route maintenance |
| 1 | John P. Hayes, Ilia Polian, Bernd Becker |
An Analysis Framework for Transient-Error Tolerance. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | George F. Viamontes, Igor L. Markov, John P. Hayes |
Checking equivalence of quantum circuits and states. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes |
Enhancing design robustness with reliability-aware resynthesis and logic simulation. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel |
Data structures and algorithms for simplifying reversible circuits. |
JETC |
2006 |
DBLP DOI BibTeX RDF |
Circuit simplification, circuit libraries, optimal subcircuit |
| 1 | Joonhwan Yi, John P. Hayes |
High-level delay test generation for modular circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramashis Das, Igor L. Markov, John P. Hayes |
On-Chip Test Generation Using Linear Subspaces. |
European Test Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. |
IEEE Trans. Parallel Distrib. Syst. |
2005 |
DBLP DOI BibTeX RDF |
distributed systems, embedded systems, Fault diagnosis, task scheduling |
| 1 | Amit Chowdhary, John P. Hayes |
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | George F. Viamontes, Igor L. Markov, John P. Hayes |
Graph-based simulation of quantum computation in the density matrix representation. |
Quantum Information & Computation |
2005 |
DBLP BibTeX RDF |
|
| 1 | Joonhwan Yi, John P. Hayes |
The Coupling Model for Function and Delay Faults. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
test generation, fault modeling, delay faults, functional faults |
| 1 | Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker |
Transient fault characterization in dynamic noisy environments. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | John P. Hayes |
Faults and Tests in Quantum Circuits. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes |
A Family of Logical Fault Models for Reversible Circuits. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
ATPG, fault models, quantum circuits, reversible circuits |
| 1 | Nagarajan Kandasamy, Sherif Abdelwahed, Gregory C. Sharp, John P. Hayes |
An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management. |
Self-star Properties in Complex Information Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
low power, linear programming, gate sizing, dual Vt |
| 1 | Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes |
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ketan N. Patel, John P. Hayes, Igor L. Markov |
Fault testing for reversible circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | John P. Hayes, Ilia Polian, Bernd Becker |
Testing for Missing-Gate Faults in Reversible Circuits. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
missing gate faults, fault models, design for test, quantum circuits, Reversible circuits |
| 1 | Rajesh Venkatasubramanian, John P. Hayes |
Discovering 1-FT Routes in Mobile Ad Hoc Networks. |
DSN |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Kandasamy, Sherif Abdelwahed, John P. Hayes |
Self-Optimization in Computer Systems via On-Line Control: Application to Power Management. |
ICAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | George F. Viamontes, Igor L. Markov, John P. Hayes |
High-Performance QuIDD-Based Simulation of Quantum Circuits. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
Exact and heuristic approaches to input vector control for leakage power reduction. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
On the properties of the input pattern fault model. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
fault testing, testing digital circuits, ATPG, fault models, faults, defects |
| 1 | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes |
Synthesis of reversible logic circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
On-Line Monitor Design of Finite-State Machines. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
finite-state machine, homomorphism, on-line monitoring |
| 1 | Feng Gao, John P. Hayes |
ILP-based optimization of sequential circuits for low power. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
low power, finite-state machine, decomposition, integer linear programming |
| 1 | John P. Hayes |
Tutorial: basic concepts in quantum circuits. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
Dependable Communication Synthesis for Distributed Embedded Systems. |
SAFECOMP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ketan N. Patel, John P. Hayes, Igor L. Markov |
Fault Testing for Reversible Circuits. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray |
Low-Cost On-Line Fault Detection Using Control Flow Assertions. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Chowdhary, John P. Hayes |
General technology mapping for field-programmable gate arrays based on lookup tables. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis |
| 1 | Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra |
Guest Editorial. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | John P. Hayes |
Fault-Tolerant Quantum Computers. (PDF / PS) |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
Time-Constrained Failure Diagnosis in Distributed Embedded Systems. |
DSN |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes |
Reversible Logic Circuit Synthesis. |
IWLS |
2002 |
DBLP BibTeX RDF |
|
| 1 | Feng Gao, John P. Hayes |
On-Line Monitor Design of Finite-State Machines. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes |
Reversible logic circuit synthesis. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyungwon Kim, John P. Hayes |
Realization-independent ATPG for designs with unimplemented blocks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes |
Fast and accurate timing characterization using functionalinformation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyungwon Kim, John P. Hayes |
Delay fault testing of IP-based designs via symbolic path modeling. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes |
An Advanced Timing Characterization Method Using Mode Dependency. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Avaneendra Gupta, John P. Hayes |
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
CMOS networks, circuit clustering, diffusion sharing, leaf cell synthesis, transistor chains, two-dimensional layout, integer programming, integer linear programming, layout optimization, module generation |
| 1 | Ronald D. Blanton, John P. Hayes |
On the design of fast, easily testable ALU's. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Hussain Al-Asaad, John P. Hayes |
Logic Design Validation via Simulation and Automatic Test Pattern Generation. |
J. Electronic Testing |
2000 |
DBLP DOI BibTeX RDF |
test generation, logic design, fault simulation, error modeling, design validation |
| 1 | David Van Campenhout, Trevor N. Mudge, John P. Hayes |
Collection and Analysis of Microprocessor Design Errors. |
IEEE Design & Test of Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Hussain Al-Asaad, John P. Hayes |
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
error and fault simulation, error modeling, Design validation, critical path tracing |
| 1 | Mark C. Hansen, Hakan Yalcin, John P. Hayes |
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. |
IEEE Design & Test of Computers |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyungwon Kim, John P. Hayes |
Delay fault testing of IP-based designs via symbolic path modeling. |
ITC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. (PDF / PS) |
SRDS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | David Van Campenhout, Trevor N. Mudge, John P. Hayes |
High-Level Test Generation for Design Verification of Pipelined Microprocessors. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
high-level test generation, pipelined microprocessors, sequential test generation, design verification |
| 1 | Hyungwon Kim, John P. Hayes |
Delay Fault Testing of Designs with Embedded IP Cores. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Avaneendra Gupta, John P. Hayes |
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown |
High-level design verification of microprocessors via error modeling. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
design verification, error modeling, design errors |
| 1 | Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes |
Optimal Zero-Aliasing Space Compaction of Test Responses. |
IEEE Trans. Computers |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chakrabarty, John P. Hayes |
Zero-aliasing space compaction of test responses using multiple parity signatures. |
IEEE Trans. VLSI Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Hussain Al-Asaad, John P. Hayes, Brian T. Murray |
Scalable Test Generators for High-Speed Datapath Circuits. |
J. Electronic Testing |
1998 |
DBLP DOI BibTeX RDF |
datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead |
| 1 | Hussain Al-Asaad, Brian T. Murray, John P. Hayes |
Online BIST for Embedded Systems. |
IEEE Design & Test of Computers |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyungwon Kim, John P. Hayes |
High-coverage ATPG for datapath circuits with unimplemented blocks. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Avaneendra Gupta, John P. Hayes |
Optimal 2-D cell layout with integrated transistor folding. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung-Kuei Ku, John P. Hayes |
Connective Fault Tolerance in Multiple-Bus Systems. |
IEEE Trans. Parallel Distrib. Syst. |
1997 |
DBLP DOI BibTeX RDF |
interconnection methods, fault tolerance, multiprocessors, graph models, Multiple-bus systems |
| 1 | Hakan Yalcin, John P. Hayes |
Event propagation conditions in circuit delay computation. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
delay computation, event propagation, propagation condition, waveform modeling, timing analysis, false path, path sensitization |
| 1 | Hung-Kuei Ku, John P. Hayes |
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses. |
IEEE Trans. Computers |
1997 |
DBLP DOI BibTeX RDF |
interconnection method, multiple-bus architecture, point-to-point connection, Fault tolerance, VLSI design, graph model |
| 1 | Krishnendu Chakrabarty, John P. Hayes |
On the quality of accumulator-based compaction of test responses. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | R. D. (Shawn) Blanton, John P. Hayes |
Testability Properties of Divergent Trees. |
J. Electronic Testing |
1997 |
DBLP DOI BibTeX RDF |
regular circuits, interactive logic arrays, structured circuits, test generation, fault detection, fault modeling |
| 1 | Avaneendra Gupta, John P. Hayes |
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Chowdhary, John P. Hayes |
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. |
FPGA |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Avaneendra Gupta, John P. Hayes |
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. |
VLSI Design |
1997 |
DBLP BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
The input pattern fault model and its application. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
Properties of the Input Pattern Fault Model. |
ICCD |
1997 |
DBLP BibTeX RDF |
|
| 1 | Frank Harary, John P. Hayes |
Node fault tolerance in graphs. |
Networks |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung-Kuei Ku, John P. Hayes |
Optimally edge fault-tolerant trees. |
Networks |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
Testability of Convergent Tree Circuits. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chakrabarty, John P. Hayes |
Test response compaction using multiplexed parity trees. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian T. Murray, John P. Hayes |
Testing ICs: Getting to the Core of the Problem. |
IEEE Computer |
1996 |
DBLP DOI BibTeX RDF |
|
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