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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4 occurrences of 4 keywords
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Found 12 publication records. Showing 12 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jongwook Jeon, Ickhyun Song, Jong Duk Lee, Byung-Gook Park, Hyungcheol Shin |
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design.  |
IEICE Transactions  |
2009 |
DBLP BibTeX RDF |
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| 1 | Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park |
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
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| 1 | Doo-Hyun Kim, Il Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park |
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
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| 1 | Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park |
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
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| 1 | Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park |
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
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| 1 | Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park |
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Seongjae Cho, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park |
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Seongjae Cho, Jang-Gn Yun, Il Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park |
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park |
Design and Simulation of Asymmetric MOSFETs. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Hyuck In Kwon, In Man Kang, Byung-Gook Park, Jong Duk Lee, Sang Sik Park, Jung Chak Ahn, Yong Hee Lee |
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements. |
Microelectronics Reliability |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Woo Young Choi, Jong Duk Lee, Byung-Gook Park |
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
RODOS, offset spacer, reverse-order, low-power, high-speed, low-noise, amplifier |
| 1 | Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park |
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
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