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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 13 keywords
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Results
Found 17 publication records. Showing 17 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Liang Tang, Jorgen Peddersen, Sri Parameswaran |
A Rapid Methodology for Multi-mode Communication Circuit Generation.  |
VLSI Design  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Su Myat Min, Jorgen Peddersen, Sri Parameswaran |
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran |
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. |
Design Autom. for Emb. Sys. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Karin Avnit, Arcot Sowmya, Jorgen Peddersen |
ACS: Automatic Converter Synthesis for SoC Bus Protocols. |
TACAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
miss rate, simulation, round robin, cache simulation, L1 cache |
| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
Improved Architectures for Range Encoding in Packet Classification System. |
NCA |
2010 |
DBLP DOI BibTeX RDF |
Range Encoding, LOP, Packet Classification |
| 1 | Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran |
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. |
DIPES/BICC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. |
DATE |
2010 |
DBLP BibTeX RDF |
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| 1 | Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran |
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. |
DATE |
2010 |
DBLP BibTeX RDF |
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| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP_RE: Range encoding for low power packet classification. |
LCN |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
low-power, packet classification, hardware design |
| 1 | Jorgen Peddersen, Sri Parameswaran |
Energy Driven Application Self-Adaptation at Run-time. |
JCP |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Jorgen Peddersen, Sri Parameswaran |
Low-Impact Processor for Dynamic Runtime Power Management. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
low-impact processor, runtime power management, power estimation, energy aware, macromodeling, counters |
| 1 | Jorgen Peddersen, Sri Parameswaran |
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption |
| 1 | Jorgen Peddersen, Sri Parameswaran |
Energy Driven Application SelfAdaptation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran |
Rapid Embedded Hardware/Software System Generation. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #17 of 17 (100 per page; Change: )
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