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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 9 keywords
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Results
Found 30 publication records. Showing 30 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | José L. Ayala, David Atienza Alonso, Ricardo Reis (eds.) |
VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers  |
VLSI-SoC (Selected Papers)  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Ignacio Arnaldo, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo |
Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens (eds.) |
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011 |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP BibTeX RDF |
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| 1 | David Cuesta Gómez, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo |
A combination of evolutionary algorithm and mathematical programming for the 3d thermal-aware floorplanning problem. |
GECCO |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor |
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mohamed M. Sabry, José L. Ayala, David Atienza |
Thermal-Aware Compilation for Register Window-Based Embedded Processors. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | José L. Ayala, Arvind Sridhar, David Cuesta |
Thermal modeling and analysis of 3D multi-processor chips. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | David Cuesta, José L. Ayala, José Ignacio Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii |
Adaptive Task Migration Policies for Thermal Control in MPSoCs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Mohamed M. Sabry, José L. Ayala, David Atienza |
Thermal-aware compilation for system-on-chip processing architectures. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
compiler, register-file, thermal-aware |
| 1 | José Luis Ayala, Cándido Méndez, Marisa López-Vallejo |
Thermal analysis and modeling of embedded processors. |
Computers & Electrical Engineering |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii |
Thermal-aware floorplanning exploration for 3D multi-core architectures. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
3D, floorplanning, MPSoC, temperature |
| 1 | Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing |
Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures. |
VLSI-SoC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici |
Dynamic thermal management in 3D multicore architectures. |
DATE |
2009 |
DBLP BibTeX RDF |
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| 1 | José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici |
Through Silicon Via-Based Grid for Thermal Control in 3D Chips. |
NanoNet |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, David Atienza, Philip Brisk |
Thermal-aware data flow analysis. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
compiler, thermal management |
| 1 | Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo |
Power Considerations in Banked CAMs: A Leakage Reduction Approach. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan |
Reliability-aware design for nanometer-scale devices. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum |
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. |
IJES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest |
Energy-aware compilation and hardware design for VLIW embedded systems. |
IJES |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo |
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Pablo Ituero, José L. Ayala, Marisa López-Vallejo |
Leakage-based On-Chip Thermal Sensor for CMOS Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio |
Thermal Characterization and Thermal Management in Processor-Based Systems. |
Power-aware Computing Systems |
2007 |
DBLP BibTeX RDF |
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| 1 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Compiler-Driven Leakage Energy Reduction in Banked Register Files. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | José Luis Ayala, Marisa López-Vallejo |
Integrating functional and power simulation in embedded systems design. |
J. Embedded Computing |
2005 |
DBLP BibTeX RDF |
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| 1 | José Luis Ayala, Marisa López-Vallejo |
Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. |
Power-aware Computing Systems |
2005 |
DBLP BibTeX RDF |
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| 1 | José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo |
Power-Aware Compilation for Register File Energy Reduction. |
International Journal of Parallel Programming |
2003 |
DBLP DOI BibTeX RDF |
register file management, compiler support, energy aware |
| 1 | José L. Ayala, Marisa Luisa López-Vallejo |
A Unified Framework for Power-Aware Design of Embedded Systems. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez |
Energy Aware Register File Implementation through Instruction Predecode. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
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