| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez |
Digital Adaptive Calibration of Multi-Step Analog to Digital Converters.  |
J. Low Power Electronics  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez |
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez |
Sliding-Mode Control to Compensate PVT Variations in dual core systems. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs |
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, José Pineda de Gyvez |
A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez |
Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor |
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez |
Body bias driven design synthesis for optimum performance per area. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt |
A forward body bias generator for digital CMOS circuits with supply voltage scaling. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Reza Pourshaghaghi, José Pineda de Gyvez |
Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, José Pineda de Gyvez |
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Reza Pourshaghaghi, José Pineda de Gyvez |
Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian M. Londono, José Pineda de Gyvez |
An energy-aware multiplier based on a Configurable-Reuse of points design methodology. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, José Pineda de Gyvez |
Calibration and Debugging of Multi-step Analog to Digital Converters. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
multi-step ADC, debugging, calibration, design-for-test |
| 1 | Amir Zjajo, José Pineda de Gyvez |
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez |
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez |
Efficient testing and diagnosis of faulty power switches in SOCs. |
IET Computers & Digital Techniques |
2007 |
DBLP BibTeX RDF |
|
| 1 | Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez |
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Josep Rius, Maurice Meijer, José Pineda de Gyvez |
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud |
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. |
J. Electronic Testing |
2006 |
DBLP DOI BibTeX RDF |
structural fault modeling, analog fault modeling, Neyman-Pearson decision, fault detection, analog test, supply current monitoring |
| 1 | Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez |
Testing and Diagnosis of Power Switches in SOCs. |
European Test Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | José Pineda de Gyvez, Guido Gronthoud, Rashid Amine |
Multi-VDD Testing for Analog Circuits. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
VDD, ramp, test, analog, IDDQ |
| 1 | Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev |
Word line pulsing technique for stability fault detection in SRAM cells. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Estella Silva, José Pineda de Gyvez, Guido Gronthoud |
Functional vs. multi-VDD testing of RF circuits. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, Hendrik J. Bergveld, Rodger Schuttert, José Pineda de Gyvez |
Power-scan chain: design for analog testability. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Josep Rius, José Pineda de Gyvez, Maurice Meijer |
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez, Ralph Otten |
On-chip digital power supply control for system-on-chip applications. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
low power, performance optimization, adaptive voltage scaling |
| 1 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Glitch-free discretely programmable clock generation on chip. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Limits to performance spread tuning using adaptive voltage and body biasing. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez |
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller |
Power Supply Ramping for Quasi-static Testing of PLLs. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Technology exploration for adaptive power and frequency scaling in 90nm CMOS. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
adaptive body bias, low power, CMOS, performance optimization, leakage, adaptive voltage scaling |
| 1 | Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek |
Low energy FPGA interconnect design. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
FPGA, low power, interconnect, encoding |
| 1 | Josep Rius Vázquez, José Pineda de Gyvez |
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek |
Low energy FPGA interconnect design. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohini Krishnan, José Pineda de Gyvez |
Low Energy Switch Block For FPGAs. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Josep Rius Vázquez, José Pineda de Gyvez |
Power Supply Noise Monitor for Signal Integrity Faults. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Phillip Christie, José Pineda de Gyvez |
Prelayout interconnect yield prediction. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio |
An Analog Integrated Circuit Design Laboratory. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | José Pineda de Gyvez, Guido Gronthoud, Rashid Amine |
VDD Ramp Testing for RF Circuits. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick |
Encoded-Low Swing Technique for Ultra Low Power Interconnect. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | José Pineda de Gyvez, Rosa Rodríguez-Montañés |
Threshold Voltage Mismatch (DeltaVT) Fault Modeling. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez |
Resistance Characterization for Weak Open Defects. |
IEEE Design & Test of Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | José Pineda de Gyvez |
Yield modeling and BEOL fundamentals. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Phillip Christie, José Pineda de Gyvez |
Pre-layout prediction of interconnect manufacturability. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
design, reliability, interconnect, theory, yield, Rent's rule, critical areas |
| 1 | José Pineda de Gyvez, Eric van de Wetering |
Average Leakage Current Estimation of CMOS Logic Circuits. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhuban Kishor, José Pineda de Gyvez |
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. (PDF / PS) |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Dornbusch, José Pineda de Gyvez |
Chaotic generation of PN sequences: a VLSI implementation. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | O. A. Gonzalez, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio |
CMOS cryptosystem using a Lorenz chaotic oscillator. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio |
Time multiplexed color image processing based on a CNN with cell-state outputs. |
IEEE Trans. VLSI Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Apollo Q. Fong, Ajay Kanji, José Pineda de Gyvez |
Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. |
Real-Time Imaging |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez |
A Universal Interface Between PC and Neural Networks Hardware. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Oscar Moreira-Tamayo, José Pineda de Gyvez |
Time Domain Analog Wavelet Transform in Real-Time. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Chi-Chien Lee, José Pineda de Gyvez |
Time-Mulitplexing CNN Simulator. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | John Willis, José Pineda de Gyvez |
Behavioral Testing of Cellular Neural Networks. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Chi-Chien Lee, José Pineda de Gyvez |
Single-Layer CNN Simulator. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | José Pineda de Gyvez, Chennian Di |
IC defect sensitivity for footprint-type spot defects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | José Pineda de Gyvez, Jochen A. G. Jess |
On the design and implementation of a wafer yield editor. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
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