Search results for "Jose Renau"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jose Renau, Will Eatherton	Hot Chips 22.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Michael Brown, Jose Renau	ReRack: power simulation for data centers with renewable energy generation.	SIGMETRICS Performance Evaluation Review	2011	DBLP DOI BibTeX RDF
1	Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau	A design time simulator for computer architects.	ISQED	2011	DBLP DOI BibTeX RDF
1	Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau	Releasing efficient beta cores to market early.	ISCA	2011	DBLP DOI BibTeX RDF
1	Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau	Characterizing processor thermal behavior.	ASPLOS	2010	DBLP DOI BibTeX RDF	microarchitecture, temperature, thermal simulation
1	Joseph Nayfach-Battilana, Jose Renau	SOI, interconnect, package, and mainboard thermal characterization.	ISLPED	2009	DBLP DOI BibTeX RDF	SOI modeling, package modeling, thermal modeling, interconnect modeling
1	Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau	Measuring and modeling variabilityusing low-cost FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	variability
1	Sangeetha Sudhakrishnan, Liying Su, Jose Renau	Processor Verification with hwBugHunt.	ISQED	2008	DBLP DOI BibTeX RDF
1	Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau	Measuring power and temperature from real processors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau	Understanding bug fix patterns in verilog.	MSR	2008	DBLP DOI BibTeX RDF	error classification, VHDL, verilog
1	Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau	Power model validation through thermal measurements.	ISCA	2007	DBLP DOI BibTeX RDF	power and thermal measurements
1	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau	Estimating design time for system circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Francisco J. Mesa-Martinez, Jose Renau	Effective Optimistic-Checker Tandem Core Design through Architectural Pruning.	MICRO	2007	DBLP DOI BibTeX RDF
1	Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau	Measuring performance, power, and temperature from real processors.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF	power and thermal measurements
1	Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	TACO	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
1	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas	Energy-Efficient Thread-Level Speculation.	IEEE Micro	2006	DBLP DOI BibTeX RDF	out-of-order task spawning, chip multiprocessors, Thread-level speculation
1	Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau	SEED: scalable, efficient enforcement of dependences.	PACT	2006	DBLP DOI BibTeX RDF	scalability, energy-efficient design, issue logic
1	Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas	POSH: a TLS compiler that exploits program structure.	PPOPP	2006	DBLP DOI BibTeX RDF	TLS compiler, profiling, prefetching, thread-level speculation, multi-core architecture
1	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau	uComplexity: Estimating Processor Design Effort.	MICRO	2005	DBLP DOI BibTeX RDF
1	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas	Thread-Level Speculation on a CMP can be energy efficient.	ICS	2005	DBLP DOI BibTeX RDF
1	Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas	Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.	ICS	2005	DBLP DOI BibTeX RDF
1	Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction.	Computer Architecture Letters	2004	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Josep Torrellas	Positional Adaptation of Processors: Application to Energy Reduction. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas	Programming the FlexRAM parallel intelligent memory system.	PPOPP	2003	DBLP DOI BibTeX RDF	compiler directives, intelligent memory architecture, programming heterogeneous computers, parallel languages
1	Michael C. Huang, Jose Renau, Josep Torrellas	Energy-efficient hybrid wakeup logic.	ISLPED	2002	DBLP DOI BibTeX RDF	wakeup logic, low power, issue logic
1	José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas	Cherry: checkpointed early resource recycling in out-of-order microprocessors.	MICRO	2002	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management.	J. Instruction-Level Parallelism	2001	DBLP BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	L1 data cache decomposition for energy efficiency.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	A framework for dynamic energy efficiency and temperature management.	MICRO	2000	DBLP DOI BibTeX RDF

Publications of "Jose Renau" ( http://dblp.L3S.de/Authors/Jose_Renau )