Search results for "Josep Torrellas"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ehsan Totoni, Babak Behzad, Swapnil Ghike, Josep Torrellas	Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs.	ISPASS	2012	DBLP DOI BibTeX RDF
1	Yuelu Duan, Xing Zhou, Wonsun Ahn, Josep Torrellas	BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks.	HPCA	2012	DBLP DOI BibTeX RDF
1	Xuehai Qian, Benjamin Sahelices, Josep Torrellas	BulkSMT: Designing SMT processors for atomic-block execution.	HPCA	2012	DBLP DOI BibTeX RDF
1	Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira, Abdullah Muzahid, Josep Torrellas	Pacman: Tolerating asymmetric data races with unintrusive hardware.	HPCA	2012	DBLP DOI BibTeX RDF
1	Josep Torrellas	Cache-Only Memory Architecture (COMA).	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Josep Torrellas	Speculation, Thread-Level.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Rishi Agarwal, Pranav Garg, Josep Torrellas	Rebound: scalable checkpointing for coherent shared memory.	ISCA	2011	DBLP DOI BibTeX RDF
1	Rishi Agarwal, Josep Torrellas	FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes.	ISCA	2011	DBLP DOI BibTeX RDF
1	Adrian Nistor, Darko Marinov, Josep Torrellas	InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing.	MICRO	2010	DBLP DOI BibTeX RDF
1	Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection.	MICRO	2010	DBLP DOI BibTeX RDF
1	Xuehai Qian, Wonsun Ahn, Josep Torrellas	ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment.	MICRO	2010	DBLP DOI BibTeX RDF
1	Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas	LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores.	HPCA	2010	DBLP DOI BibTeX RDF
1	Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime Moreno, Kunle Olukotun	Extreme scale computing: Challenges and opportunities.	HPCA	2010	DBLP DOI BibTeX RDF
1	Josep Torrellas, Bill Gropp, Jaime Moreno, Kunle Olukotun, Vivek Sarkar	Extreme scale computing: challenges and opportunities.	PPOPP	2010	DBLP DOI BibTeX RDF	architecture, challenges, exascale
1	James Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze	SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas	Two hardware-based approaches for deterministic multiprocessor replay.	Commun. ACM	2009	DBLP DOI BibTeX RDF
1	Josep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, Milos Prvulovic	The Bulk Multicore architecture for improved programmability.	Commun. ACM	2009	DBLP DOI BibTeX RDF
1	Josep Torrellas	Architectures for Extreme-Scale Computing.	IEEE Computer	2009	DBLP DOI BibTeX RDF
1	Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas	SigRace: signature-based data race detection.	ISCA	2009	DBLP DOI BibTeX RDF	SigRace, concurrency defect, signature, timestamp, data race, happened-before
1	Pablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas	Capo: a software-hardware interface for practical deterministic multiprocessor replay.	ASPLOS	2009	DBLP DOI BibTeX RDF	capo, capoone, replay sphere, deterministic replay
1	Josep Torrellas	How to build a useful thousand-core manycore system?	IPDPS	2009	DBLP DOI BibTeX RDF
1	Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, J.-W. Lee, Xing Fang, Samuel P. Midkiff, David Wong	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.	MICRO	2009	DBLP DOI BibTeX RDF	atomic region, chunk-based architecture, compiler optimization, sequential consistency
1	Adrian Nistor, Darko Marinov, Josep Torrellas	Light64: lightweight hardware support for data race detection during systematic testing of parallel programs.	MICRO	2009	DBLP DOI BibTeX RDF	execution history hash, data race, systematic testing
1	Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas	The BubbleWrap many-core: popping cores for sequential acceleration.	MICRO	2009	DBLP DOI BibTeX RDF	power wall, process scaling, processor aging, voltage scaling
1	Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles	Blueshift: Designing processors for timing speculation from the ground up.	HPCA	2009	DBLP DOI BibTeX RDF
1	Pablo Montesinos, Luis Ceze, Josep Torrellas	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently.	ISCA	2008	DBLP DOI BibTeX RDF
1	Radu Teodorescu, Josep Torrellas	Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors.	ISCA	2008	DBLP DOI BibTeX RDF
1	James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas	SoftSig: software-exposed hardware signatures for code analysis and optimization.	ASPLOS	2008	DBLP DOI BibTeX RDF	multi-core architectures, memory disambiguation, runtime optimization
1	Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, Josep Torrellas	Concurrency control with data coloring.	MSPC	2008	DBLP DOI BibTeX RDF	data coloring, concurrency control, programming model
1	Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas	EVAL: Utilizing processors with variation-induced timing errors.	MICRO	2008	DBLP DOI BibTeX RDF
1	Abhishek Tiwari, Josep Torrellas	Facelift: Hiding and slowing down aging in multicores.	MICRO	2008	DBLP DOI BibTeX RDF
1	Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas	Patching Processor Design Errors with Programmable Hardware.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware errors, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis
1	Smruti R. Sarangi, Brian Greskamp, Josep Torrellas	A Model for Timing Errors in Processors with Parameter Variation.	ISQED	2007	DBLP DOI BibTeX RDF
1	Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
1	Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas	BulkSC: bulk enforcement of sequential consistency.	ISCA	2007	DBLP DOI BibTeX RDF	bulk, chip multiprocessors, programmability, sequential consistency, memory consistency models
1	Brian Greskamp, Josep Torrellas	Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking.	PACT	2007	DBLP DOI BibTeX RDF
1	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau	Estimating design time for system circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Pablo Montesinos, Wei Liu, Josep Torrellas	Using Register Lifetime Predictions to Protect Register Files against Soft Errors.	DSN	2007	DBLP DOI BibTeX RDF
1	Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas	Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing.	MICRO	2007	DBLP DOI BibTeX RDF
1	Karin Strauss, Xiaowei Shen, Josep Torrellas	Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
1	Brian Greskamp, Smruti R. Sarangi, Josep Torrellas	Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas	Colorama: Architectural Support for Data-Centric Synchronization.	HPCA	2007	DBLP DOI BibTeX RDF
1	James Tuck, Wei Liu, Josep Torrellas	CAP: Criticality analysis for power-efficient speculative multithreading.	ICCD	2007	DBLP DOI BibTeX RDF
1	Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	TACO	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
1	Radu Teodorescu, Jun Nakano, Josep Torrellas	SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback.	IEEE Micro	2006	DBLP DOI BibTeX RDF	low-overhead checkpointing, hardware prototype, transient faults
1	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas	Energy-Efficient Thread-Level Speculation.	IEEE Micro	2006	DBLP DOI BibTeX RDF	out-of-order task spawning, chip multiprocessors, Thread-level speculation
1	Josep Torrellas	Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Top Picks, Microarchictectures Conferences, IEEE Micro
1	Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval	Bulk Disambiguation of Speculative Threads in Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
1	Karin Strauss, Xiaowei Shen, Josep Torrellas	Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
1	Josep Torrellas (eds.)	Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006	ASID	2006	DBLP BibTeX RDF
1	Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas	Accurate and efficient filtering for the Intel thread checker race detector.	ASID	2006	DBLP DOI BibTeX RDF	data-race detection
1	Smruti R. Sarangi, Brian Greskamp, Josep Torrellas	CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.	DSN	2006	DBLP DOI BibTeX RDF
1	James Tuck, Luis Ceze, Josep Torrellas	Scalable Cache Miss Handling for High Memory-Level Parallelism.	MICRO	2006	DBLP DOI BibTeX RDF
1	Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas	Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware.	MICRO	2006	DBLP DOI BibTeX RDF
1	Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas	PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection.	MICRO	2006	DBLP DOI BibTeX RDF
1	Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas	ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers.	HPCA	2006	DBLP DOI BibTeX RDF
1	Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas	POSH: a TLS compiler that exploits program structure.	PPOPP	2006	DBLP DOI BibTeX RDF	TLS compiler, profiling, prefetching, thread-level speculation, multi-core architecture
1	Josep Torrellas, Siddhartha Chatterjee (eds.)	Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2006, New York, New York, USA, March 29-31, 2006	PPOPP	2006	DBLP BibTeX RDF
1	María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas	Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors.	TACO	2005	DBLP DOI BibTeX RDF	Caching and buffering support, memory hierarchies, shared-memory multiprocessors, thread-level speculation, coherence protocol
1	Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas	Efficient and flexible architectural support for dynamic monitoring.	TACO	2005	DBLP DOI BibTeX RDF	dynamic monitoring, thread-level speculation (TLS), software debugging, Architectural support
1	Radu Teodorescu, Josep Torrellas	Prototyping Architectural Support for Program Rollback Using FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
1	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas	Thread-Level Speculation on a CMP can be energy efficient.	ICS	2005	DBLP DOI BibTeX RDF
1	Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas	Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.	ICS	2005	DBLP DOI BibTeX RDF
1	Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction.	Computer Architecture Letters	2004	DBLP DOI BibTeX RDF
1	Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas	iWatcher: Simple, General Architectural Support for Software Debugging.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas	iWatcher: Efficient Architectural Support for Software Debugging.	ISCA	2004	DBLP DOI BibTeX RDF
1	Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas	AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants.	MICRO	2004	DBLP DOI BibTeX RDF
1	José F. Martínez, Josep Torrellas	Speculative Synchronization: Programmability and Performance for Parallel Codes.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Yan Solihin, Jaejin Lee, Josep Torrellas	Correlation Prefetching with a User-Level Memory Thread.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	correlation prefetching, memory-side prefetching, intelligent memory architecture, Prefetching, heterogeneous system, processing-in-memory, helper threads
1	Michael C. Huang, Jose Renau, Josep Torrellas	Positional Adaptation of Processors: Application to Energy Reduction. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Milos Prvulovic, Josep Torrellas	ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes.	ISCA	2003	DBLP BibTeX RDF
1	Anthony-Trung Nguyen, Josep Torrellas	Design Trade-Offs in High-Throughput Coherence Controllers.	IEEE PACT	2003	DBLP DOI BibTeX RDF
1	María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation.	IEEE PACT	2003	DBLP DOI BibTeX RDF
1	María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas	Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors.	HPCA	2003	DBLP DOI BibTeX RDF
1	Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas	Programming the FlexRAM parallel intelligent memory system.	PPOPP	2003	DBLP DOI BibTeX RDF	compiler directives, intelligent memory architecture, programming heterogeneous computers, parallel languages
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas	Software Trace Cache for Commercial Applications.	International Journal of Parallel Programming	2002	DBLP DOI BibTeX RDF
1	Milos Prvulovic, Josep Torrellas, Zheng Zhang	ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	fault tolerance, availability, checkpointing, shared-memory multiprocessors, recovery, logging, BER, rollback recovery, parity
1	Yan Solihin, Josep Torrellas, Jaejin Lee	Using a User-Level Memory Thread for Correlation Prefetching. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	intelligent memory, correlation prefetching, caches, computer architecture, memory hierarchies, threads, data prefetching, processing-in-memory
1	Michael C. Huang, Jose Renau, Josep Torrellas	Energy-efficient hybrid wakeup logic.	ISLPED	2002	DBLP DOI BibTeX RDF	wakeup logic, low power, issue logic
1	José F. Martínez, Josep Torrellas	Speculative synchronization: applying thread-level speculation to explicitly parallel applications.	ASPLOS	2002	DBLP DOI BibTeX RDF
1	Francis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas	SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
1	José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas	Cherry: checkpointed early resource recycling in out-of-order microprocessors.	MICRO	2002	DBLP DOI BibTeX RDF
1	Marcelo H. Cintra, Josep Torrellas	Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors.	HPCA	2002	DBLP DOI BibTeX RDF	Shared-Memory Multiprocessors, Speculative Parallelization
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management.	J. Instruction-Level Parallelism	2001	DBLP BibTeX RDF
1	Venkata Krishnan, Josep Torrellas	The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors.	International Journal of Parallel Programming	2001	DBLP DOI BibTeX RDF
1	Yan Solihin, Jaejin Lee, Josep Torrellas	Automatic Code Mapping on an Intelligent Memory Architecture.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Intelligent memory architecture, compilers, performance prediction, heterogeneous system, processing-in-memory, adaptive execution
1	Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas	Removing architectural bottlenecks to the scalability of speculative parallelization.	ISCA	2001	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	L1 data cache decomposition for energy efficiency.	ISLPED	2001	DBLP DOI BibTeX RDF
1	María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger	Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors.	IEEE PACT	2001	DBLP DOI BibTeX RDF
1	Jaejin Lee, Yan Solihin, Josep Torrellas	Automatically Mapping Code on an Intelligent Memory Architecture.	HPCA	2001	DBLP DOI BibTeX RDF
1	Marcelo H. Cintra, José F. Martínez, Josep Torrellas	Architectural support for scalable speculative parallelization in shared-memory multiprocessors.	ISCA	2000	DBLP DOI BibTeX RDF
1	Yan Solihin, Jaejin Lee, Josep Torrellas	Adaptively Mapping Code in an Intelligent Memory Architecture.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	A framework for dynamic energy efficiency and temperature management.	MICRO	2000	DBLP DOI BibTeX RDF
1	Lawrence Rauchwerger, Nancy M. Amato, Josep Torrellas	SmartApps: An Application Centric Approach to High Performance Computing.	LCPC	2000	DBLP DOI BibTeX RDF
1	Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen	Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration.	HPCA	2000	DBLP DOI BibTeX RDF	directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA
1	Qiang Cao, Josep Torrellas, H. V. Jagadish	Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Venkata Krishnan, Josep Torrellas	A Chip-Multiprocessor Architecture with Speculative Multithreading.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Chip-multiprocessor, speculative multithreading, data-dependence speculation, control speculation
1	Zheng Zhang, Marcelo H. Cintra, Josep Torrellas	Excel-NUMA: Toward Programmability, Simplicity, and High Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	NUMA organizations, performance evaluation, caches, Shared-memory multiprocessors, cache-coherence protocols
1	Chun Xia, Josep Torrellas	Comprehensive Hardware and Software Support for Operating Systems to Exploit.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	architectural support for operating system, block operations, performance, prefetching, shared-memory multiprocessors, trace-driven simulations, Cache hierarchies

Publications of "Josep Torrellas" ( http://dblp.L3S.de/Authors/Josep_Torrellas )