| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Predrag Radosavljevic, Kyeong Jin Kim, Hao Shen, Joseph R. Cavallaro |
Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems.  |
IEEE Transactions on Signal Processing  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture. |
IEEE Transactions on Signal Processing |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang (eds.) |
Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012 |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP BibTeX RDF |
|
| 1 | Kiarash Amiri, Michael Wu, Joseph R. Cavallaro, Jorma Lilleberg |
Cooperative Partial Detection Using MIMO Relays. |
IEEE Transactions on Signal Processing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Myllylä, Joseph R. Cavallaro, Markku J. Juntti |
Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
A Flexible LDPC/Turbo Decoder Architecture. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Wu, Yang Sun, Siddharth Gupta, Joseph R. Cavallaro |
Implementation of a High Throughput Soft MIMO Detector on GPU. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiarash Amiri, Joseph R. Cavallaro, Chris Dick, Raghu Mysore Rao |
A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Wu, Yang Sun, Guohui Wang, Joseph R. Cavallaro |
Implementation of a High Throughput 3GPP Turbo Decoder on GPU. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Guohui Wang, Yang Sun, Joseph R. Cavallaro, Yuanbin Guo |
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca (eds.) |
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 |
ASAP |
2011 |
DBLP BibTeX RDF |
|
| 1 | Yang Sun, Guohui Wang, Joseph R. Cavallaro |
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Myllylä, Markku J. Juntti, Joseph R. Cavallaro |
Implementation aspects of list sphere decoder algorithms for MIMO-OFDM systems. |
Signal Processing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Johanna Ketonen, Markku J. Juntti, Joseph R. Cavallaro |
Performance: complexity comparison of receivers for a LTE MIMO-OFDM system. |
IEEE Transactions on Signal Processing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiarash Amiri, Michael Wu, Melissa Duarte, Joseph R. Cavallaro |
Physical layer algorithm and hardware verification of MIMO relays using cooperative partial detection. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
Low-complexity and high-performance soft MIMO detection based on distributed M-algorithm through trellis-diagram. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro |
Programming high performance signal processing systems in high level languages. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
high level programming models, fpga, signal processing, dsp |
| 1 | Predrag Radosavljevic, Yuanbin Guo, Joseph R. Cavallaro |
Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture. |
IEEE Journal on Selected Areas in Communications |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Myllylä, Markku J. Juntti, Joseph R. Cavallaro |
Architecture design and implementation of the increasing radius - List sphere detector algorithm. |
ICASSP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Wu, Siddharth Gupta, Yang Sun, Joseph R. Cavallaro |
A GPU implementation of a real-time MIMO detector. |
SiPS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
mimo detection, VLSI architecture, ASIC design |
| 1 | Kiarash Amiri, Joseph R. Cavallaro |
Partial detection for multiple antenna cooperation. |
CISS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro, Tai Ly |
Scalable and low power LDPC decoder design using high level algorithmic synthesis. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro |
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. |
IJES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro |
Configurable LDPC Decoder Architectures for Regular and Irregular Codes. |
Signal Processing Systems |
2008 |
DBLP DOI BibTeX RDF |
Error correcting codes, Reconfigurable architectures, Low density parity check codes |
| 1 | Sridhar Rajagopal, Joseph R. Cavallaro |
Communication Processors for Wireless Systems. |
Wiley Encyclopedia of Computer Science and Engineering |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Predrag Radosavljevic, Joseph R. Cavallaro |
Design of block-structured LDPC codes for iterative receivers with soft sphere detection. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
Unified decoder architecture for LDPC/turbo codes. |
SiPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Marjan Karkooti, Joseph R. Cavallaro |
Cooperative Communications Using Scalable, Medium Block-length LDPC Codes. |
WCNC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiarash Amiri, Davood Shamsi, Behnaam Aazhang, Joseph R. Cavallaro |
Adaptive codebook for beamforming in limited feedback MIMO systems. |
CISS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Cavallaro |
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiarash Amiri, Chris Dick, Raghu Mysore Rao, Joseph R. Cavallaro |
Novel Sort-Free Detector with Modified Real-Valued Decomposition (M-RVD) Ordering in MIMO Systems. |
GLOBECOM |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Predrag Radosavljevic, Kyeong Jin Kim, Joseph R. Cavallaro |
QRD-QLD Searching Based Sphere Detection for Emerging MIMO Downlink OFDM Receivers. |
GLOBECOM |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph R. Cavallaro, Sanjay Rajopadhye, Lothar Thiele, Tobias Noll |
Special Issue on ASAP 2004 Conference. |
VLSI Signal Processing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Myllylä, Markku J. Juntti, Joseph R. Cavallaro |
Implementation Aspects of List Sphere Detector Algorithms. |
GLOBECOM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Marjan Karkooti, Joseph R. Cavallaro |
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanbin Guo, Jianzhong (Charlie) Zhang, Dennis McCain, Joseph R. Cavallaro |
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture. |
EURASIP J. Adv. Sig. Proc. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis Demestichas, Guillaume Vivier, Joseph R. Cavallaro |
Special Issue on Reconfigurable Radio Technologies in Support of Ubiquitous Seamless Computing. |
MONET |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro, Andres Takach |
Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology. |
EURASIP J. Emb. Sys. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rajagopal, Joseph R. Cavallaro |
Truncated Online Arithmetic with Applications to Communication Systems. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Dynamic truncation, finite precision, communication systems, online arithmetic |
| 1 | Yuanbin Guo, Joseph R. Cavallaro |
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems. |
VLSI Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
adaptive, VLSI, low power, SoC, CDMA, interference cancellation |
| 1 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro |
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Predrag Radosavljevic, Alexandre de Baynast, Marjan Karkooti, Joseph R. Cavallaro |
Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area. |
PIMRC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Myllylä, Pirkka Silvola, Markku J. Juntti, Joseph R. Cavallaro |
Comparison of Two Novel List Sphere Detector Algorithms for MIMO-OFDM Systems. |
PIMRC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Das, Elza Erkip, Joseph R. Cavallaro, Behnaam Aazhang |
Low-complexity iterative multiuser detection and decoding for real-time applications. |
IEEE Transactions on Wireless Communications |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Manik Gadhiok, Ricky Hardy, Patrick Murphy, J. Patrick Frantz, Hyeokho Choi, Joseph R. Cavallaro |
An FPGA-Based Daughtercard for TI's C6000 family of DSKs. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner |
Design Space Exploration for Real-Time Embedded Stream Processors. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro |
Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Marjan Karkooti, Joseph R. Cavallaro |
Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding. |
ITCC |
2004 |
DBLP DOI BibTeX RDF |
FPGA imple-mentation, area-time tradeoffs, parallel architecture, Reconfigurable architecture, channel coding |
| 1 | Bryan A. Jones, Joseph R. Cavallaro |
A Rapid Prototyping Environment for Wireless Communication Embedded Systems. |
EURASIP J. Adv. Sig. Proc. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Murphy, J. Patrick Frantz, Erik Welsh, Ricky Hardy, Tinoosh Mohsenin, Joseph R. Cavallaro |
VALID: Custom ASIC Verification and FPGA Education Platform. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro |
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA. |
IEEE International Workshop on Rapid System Prototyping |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro |
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers. |
IEEE Transactions on Wireless Communications |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Gang Xu, Sridhar Rajagopal, Joseph R. Cavallaro, Behnaam Aazhang |
VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers. |
VLSI Signal Processing |
2002 |
DBLP DOI BibTeX RDF |
multistage detector, CDMA, fixed-point, multiuser detection, interference cancellation, real-time implementation |
| 1 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers. |
VLSI Signal Processing |
2002 |
DBLP DOI BibTeX RDF |
multiuser channel estimation, VLSI, DSP, fixed-point, dependence graphs, W-CDMA, real-time implementation |
| 1 | Martin L. Leuschen, Joseph R. Cavallaro, Ian D. Walker |
Robotic Fault Detection using Nonlinear Analytical Redundancy. |
ICRA |
2002 |
DBLP BibTeX RDF |
|
| 1 | Yuanbin Guo, Joseph R. Cavallaro |
A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanbin Guo, Joseph R. Cavallaro |
Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Livingston, Vikram Chandrasekhar, M. Vaya, Joseph R. Cavallaro |
Handset detector architectures for DS-CDMA wireless systems. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chaitali Sengupta, Joseph R. Cavallaro, Behnaam Aazhang |
On multipath channel estimation for CDMA systems using multiple sensors. |
IEEE Transactions on Communications |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rajagopal, Joseph R. Cavallaro |
A bit-streaming, pipelined multiuser detector for wireless communication receivers. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rajagopal, Joseph R. Cavallaro |
On-line Arithmetic for Detection in Digital Communication Receivers. |
IEEE Symposium on Computer Arithmetic |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
real-time, Wireless communications, DSP, VLSI architecture, wideband CDMA, channel estimation |
| 1 | Ian D. Walker, Joseph R. Cavallaro, Martin L. Leuschen |
Keeping the Analog Genie in the Bottle: A Case for Digital Robots. |
ICRA |
1999 |
DBLP BibTeX RDF |
|
| 1 | B. Haller, J. Goetze, Joseph R. Cavallaro |
Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Ian D. Walker, Joseph R. Cavallaro |
Parallel VLSI architectures for real-time kinematics of redundant robots. |
Journal of Intelligent and Robotic Systems |
1994 |
DBLP DOI BibTeX RDF |
cordic arithmetic, kinematic redundancy, VLSI, Robot kinematics, pseudoinverse |
| 1 | Nariankadu D. Hemkumar, Joseph R. Cavallaro |
Redundant and On-Line CORDIC for Unitary Transformations. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
unitary transformations, two-sided unitary transformation, Jacobi-like methods, complex matrices, special-purpose processor array architectures, nonredundant CORDIC, online CORDIC, redundant CORDIC, Coordinate Rotation Digital Computer, parallel algorithms, parallel algorithms, computational complexity, parallel architectures, singular value decompositions, digital arithmetic, matrix algebra, eigenvalue, CORDIC, special purpose computers, eigenvalues and eigenfunctions, matrices |
| 1 | M. L. Visinsky, Ian D. Walker, Joseph R. Cavallaro |
New Dynamic Model-Based Fault Detection Thresholds for Robot Manipulators. |
ICRA |
1994 |
DBLP BibTeX RDF |
|
| 1 | Kishore Kota, Joseph R. Cavallaro |
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
numerical accuracy, hardware tradeoffs, CORDIC arithmetic, special-purpose processors, coordinate rotation digital computer, real-time signal processing, Y-reduction mode, inverse tangent function, floating-point CORDIC, special-purpose arrays, signal processing, digital arithmetic, hybrid architecture, implementation complexity |
| 1 | M. L. Visinsky, Ian D. Walker, Joseph R. Cavallaro |
Layered Dynamic Fault Detection and Tolerance for Robots. |
ICRA |
1993 |
DBLP BibTeX RDF |
|
| 1 | Ian D. Walker, Joseph R. Cavallaro |
Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots. |
ICRA |
1993 |
DBLP BibTeX RDF |
|
| 1 | Nariankadu D. Hemkumar, Joseph R. Cavallaro |
Efficient complex matrix transformations with CORDIC. |
IEEE Symposium on Computer Arithmetic |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Arati S. Deo, Joseph R. Cavallaro, Ian D. Walker |
New Real-Time Robot Motion Algorithms Using Parallel VLSI Architectures. |
PPSC |
1991 |
DBLP BibTeX RDF |
|
| 1 | Joseph R. Cavallaro, Franklin T. Luk |
CORDIC Arithmetic for an SVD Processor. |
J. Parallel Distrib. Comput. |
1988 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph R. Cavallaro, Franklin T. Luk |
CORDIC arithmetic for an SVD processor. |
IEEE Symposium on Computer Arithmetic |
1987 |
DBLP DOI BibTeX RDF |
|
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