|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 31 occurrences of 24 keywords
|
|
|
|
|
Results
Found 49 publication records. Showing 49 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | José L. Risco-Martín, Juan Lanchares, Carlos A. Coello Coello |
Special issue on evolutionary computation on general purpose graphics processing units.  |
Soft Comput.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo |
A phase adaptive cache hierarchy for SMT processors. |
Microprocessors and Microsystems - Embedded Hardware Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Francisco Fernández, Juan Lanchares, Erick Cantú-Paz, Albert Y. Zomaya |
Parallel Architectures and Bioinspired Algorithms. |
Parallel Computing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares |
Parallel and Distributed Optimization of Dynamic Data Structures for Multimedia Embedded Systems. |
Parallel and Distributed Computational Intelligence |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | José Manuel Colmenar, José L. Risco-Martín, David Atienza, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares |
Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. |
GECCO |
2010 |
DBLP DOI BibTeX RDF |
genetic programming, evolutionary computation, embedded systems design, grammatical evolution |
| 1 | Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo |
Adaptive Cache Memories for SMT Processors. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo |
Simulating a LAGS processor to consider variable latency on L1 D-Cache. |
SummerSim |
2010 |
DBLP BibTeX RDF |
|
| 1 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo |
Characterizing asynchronous variable latencies through probability distribution functions. |
Microprocessors and Microsystems - Embedded Hardware Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos Baloukas, José Luis Risco-Martín, David Atienza, Christophe Poucet, Lazaros Papadopoulos, Stylianos Mamagkakis, Dimitrios Soudris, José Ignacio Hidalgo, Francky Catthoor, Juan Lanchares |
Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems. |
Journal of Systems and Software |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | José Luis Risco-Martín, José Ignacio Hidalgo, David Atienza, Juan Lanchares, Oscar Garnica |
Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems. |
GECCO |
2009 |
DBLP DOI BibTeX RDF |
evolutionary computation, particle swarm optimization, multi-objective optimization, mathematical programming, embedded systems design |
| 1 | José L. Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares |
A parallel evolutionary algorithm to optimize dynamic data types in embedded systems. |
Soft Comput. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Risco-Martín, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, David Atienza |
Particle swarm optimisation of memory usage in embedded systems. |
IJHPSA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, José L. Risco-Martín, David Atienza, Juan Lanchares |
Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems. |
GECCO |
2008 |
DBLP DOI BibTeX RDF |
evolutionary computation, multi-objective optimization, embedded systems design, pareto optimal front |
| 1 | José L. Risco-Martín, José Ignacio Hidalgo, Juan Lanchares, Oscar Garnica |
Solving discrete deceptive problems with EMMRS. |
GECCO |
2008 |
DBLP DOI BibTeX RDF |
deceptive problems, genotype and phenotype mapping, genetic algorithms |
| 1 | José Luis Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares |
Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo |
Modelling Asynchronous Systems using Probability Distribution Functions. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
modelling, asynchronous, microarchitecture |
| 1 | Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López |
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Juan Lanchares, Francisco Fernández de Vega, Daniel Lombraña Gonzalez |
Is the island model fault tolerant? |
GECCO (Companion) |
2007 |
DBLP DOI BibTeX RDF |
distrbuted gas, fault-tolerant |
| 1 | José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Daniel Lombraña Gonzalez |
Is the island model fault tolerant? |
GECCO |
2007 |
DBLP DOI BibTeX RDF |
distributed GAs, fault-tolerant |
| 1 | Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares |
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | David Atienza, Christos Baloukas, Lazaros Papadopoulos, Christophe Poucet, Stylianos Mamagkakis, José Ignacio Hidalgo, Francky Catthoor, Dimitrios Soudris, Juan Lanchares |
Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. |
SCOPES |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares |
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López |
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. |
Euro-Par |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López |
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López |
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar |
A Power-Aware Technique for Functional Units in High-Performance Processors. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar |
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Francisco Fernández, José Ignacio Hidalgo, Juan Lanchares, J. M. Sánchez |
A methodology for reconfigurable hardware design based upon evolutionary computation. |
Microprocessors and Microsystems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan de Vicente, Juan Lanchares, Román Hermida |
Annealing placement by thermodynamic combinatorial optimization. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
Recofigurable, combinatorial optimization, entropy, information theory, programmable logic, thermodynamics |
| 1 | José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida |
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. |
PDP |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica |
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. |
GECCO |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida |
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Ranieri Baraglia, Francisco Tirado, Oscar Garnica |
Hybrid Parallelization of a Compact Genetic Algorithm. |
PDP |
2003 |
DBLP DOI BibTeX RDF |
Local search, graph-partitioning, Compact Genetic Algorithm, Hybrid parallelization |
| 1 | Oscar Garnica, Juan Lanchares, Román Hermida |
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. |
Fundam. Inform. |
2002 |
DBLP BibTeX RDF |
|
| 1 | Oscar Garnica, Juan Lanchares, Román Hermida |
A New Methodology to Design Low-Power Asynchronous Circuits. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida |
Optimization of Equational Specifications Using Genetic Techniques. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida |
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida |
Transformation of Equational Specification by Means of Genetic Programming. |
EuroGP |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan de Vicente, Juan Lanchares, Román Hermida |
FPGA Placement by Thermodynamic Combinatorial Optimization. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Oscar Garnica, Juan Lanchares, Román Hermida |
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. |
ACSD |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz |
Pipelined Genetic Architecture with Fitness on the Fly. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Oscar Garnica, Juan Lanchares, Román Hermida |
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ranieri Baraglia, Raffaele Perego, José Ignacio Hidalgo, Juan Lanchares, Francisco Tirado |
A Parallel Compact Genetic Algorithm for Multi-FPGA Partitioning. |
PDP |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan de Vicente, Juan Lanchares, Román Hermida |
Adaptive FPGA Placement by Natural Optimization. (PDF / PS) |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
Combinatorial optimization, reconfigurable, placement |
| 1 | José Ignacio Hidalgo, Juan Lanchares, Román Hermida |
Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. |
EUROMICRO |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan de Vicente, Juan Lanchares, Román Hermida |
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. |
FPL |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Francisco Tirado, B. de Andrés, S. Esteban, D. Rivera |
A Method for Model Parameter Identification Using Parallel Genetic Algorithms. |
PVM/MPI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan de Vicente, Juan Lanchares, Román Hermida |
RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | José Ignacio Hidalgo, Juan Lanchares |
Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #49 of 49 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")