Search results for "Jude A. Rivers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger	Power management of multi-core chips: Challenges and pitfalls.	DATE	2012	DBLP BibTeX RDF
1	Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose	Error Tolerance in Server Class Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie	Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.	ICCD	2011	DBLP DOI BibTeX RDF
1	Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban	Power-efficient, reliable microprocessor architectures: modeling and design methods.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power-efficient design, pre-silicon modeling, reliable operation
1	Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee	SAFER: Stuck-At-Fault Error Recovery for Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Prabhakar Kudva	Reliability Challenges and System Performance at the Architecture Level.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers	Scalable high performance main memory system using phase-change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	dram caching, phase change memory, wear leveling
1	Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks	Tribeca: design for PVT variations with local recovery and fine-grained adaptation.	MICRO	2009	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves	Phaser: Phased methodology for modeling the system-level effects of soft errors.	IBM Journal of Research and Development	2008	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Online Estimation of Architectural Vulnerability Factor for Soft Errors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Metrics for Architecture-Level Lifetime Reliability Analysis.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose	A Framework for Architecture-Level Lifetime Reliability Modeling.	DSN	2007	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions.	DSN	2007	DBLP DOI BibTeX RDF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Lifetime Reliability: Toward an Architectural Solution.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Lifetime reliability, RAMP, power management, scaling, DRM, MTTF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Exploiting Structural Duplication for Lifetime Reliability Enhancement.	ISCA	2005	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors.	DSN	2005	DBLP DOI BibTeX RDF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	The Case for Lifetime Reliability-Aware Microprocessors.	ISCA	2004	DBLP DOI BibTeX RDF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	The Impact of Technology Scaling on Lifetime Reliability.	DSN	2004	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno	Reducing instruction fetch energy with backwards branch control information and buffering.	ISLPED	2003	DBLP DOI BibTeX RDF	loop buffer, low-power, instruction fetch
1	Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson	Active Management of Data Caches by Exploiting Reuse Information.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Multilateral cache, reuse information, active management
1	Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson	mlcache: A Flexible Multi-Lateral Cache Simulator. (PDF / PS)	MASCOTS	1998	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens	Utilizing Reuse Information in Data Cache Management.	International Conference on Supercomputing	1998	DBLP DOI BibTeX RDF	effective address, multi-lateral caches, program counter
1	Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin	On High-Bandwidth Data Cache Design for Multi-Issue Processors.	MICRO	1997	DBLP BibTeX RDF	Locality-Based Interleaving, Multiporting, High-Bandwidth Data Supply, Multi-Bank Caches
1	Jude A. Rivers, Edward S. Tam, Edward S. Davidson	On Effective Data Supply For Multi-Issue Processors.	ICCD	1997	DBLP BibTeX RDF
1	Jude A. Rivers, Edward S. Davidson	Performance Issues in Integrating Temporality-Based Caching with Prefetching.	Perform. Eval.	1996	DBLP BibTeX RDF
1	Jude A. Rivers, Edward S. Davidson	Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design.	ICPP, Vol. 1	1996	DBLP BibTeX RDF

Publications of "Jude A. Rivers" ( http://dblp.L3S.de/Authors/Jude_A._Rivers )