Search results for "Juha Plosila"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Masoud Daneshtalab, Masoumeh Kamali, Masoumeh Ebrahimi, S. Mohammadi, Ali Afzali-Kusha, Juha Plosila	Adaptive Input-Output Selection Based On-Chip Router Architecture.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	K. Somasundaram, Juha Plosila	Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip.	IJERTCS	2012	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Memory-Efficient On-Chip Network With Adaptive Interfaces.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Ville Rantala, Pasi Liljeberg, Juha Plosila	Status Data and Communication Aspects in Dynamically Clustered Network-on-Chip Monitoring.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Khalid Latif 0002, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.	DATE	2012	DBLP BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.	PDP	2012	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture.	PDP	2012	DBLP DOI BibTeX RDF
1	Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila	Analysis of Monitoring Structures for Network-on-Chip: A Distributed Approach.	IJERTCS	2011	DBLP BibTeX RDF
1	Amir-Mohammad Rahmani, Khalid Latif 0002, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power-Efficient Inter-Layer Communication Architectures for 3D NoC.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Kameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila	Thermal Analysis of Advanced 3D Stacked Systems.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila	Q-learning based congestion-aware routing algorithm for on-chip network.	NESEA	2011	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Khalid Latif 0002, Juha Plosila, Kameswar Rao Vaddina, Hannu Tenhunen	Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures.	NOCS	2011	DBLP BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.	NOCS	2011	DBLP BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture.	DSD	2011	DBLP DOI BibTeX RDF
1	Kameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila	Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's.	DSD	2011	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Agent-based on-chip network using efficient selection method.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen	Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.	FPT	2011	DBLP DOI BibTeX RDF
1	Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen	Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Cluster-based topologies for 3D stacked architectures.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila	Analysis of Status Data Update in Dynamically Clustered Network-on-chip Monitoring.	PECCS	2011	DBLP BibTeX RDF
1	Liang Guang, Bo Yang, Juha Plosila, Jouni Isoaho, Hannu Tenhunen	Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems.	PECCS	2011	DBLP BibTeX RDF
1	Amir-Mohammad Rahmani, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication.	PDP	2011	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	High-performance on-chip network platform for memory-on-processor architectures.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Mohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila	Exploration of MPSoC monitoring and management systems.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Efficient congestion-aware selection method for on-chip networks.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Liang Guang, Juha Plosila, Jouni Isoaho, Hannu Tenhunen	Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila	Modeling Communication in Multi-Processor Systems-on-Chip Using Modular Connectors.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Jouni Isoaho, Seppo Virtanen, Juha Plosila	Current Challenges in Embedded Communication Systems.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Teijo Lehtonen, David Wolpert, Pasi Liljeberg, Juha Plosila, Paul Ampadu	Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Process variation tolerant on-chip communication using receiver and driver reconfiguration.	ISQED	2010	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	High-Performance TSV Architecture for 3-D ICs.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Input-Output Selection Based Router for Networks-on-Chip.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	A Low-Latency and Memory-Efficient On-chip Network.	NOCS	2010	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.	PDP	2010	DBLP DOI BibTeX RDF	AXI protocol, Network on Chip, Buffer Management, Network Interface
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	CMIT - A novel cluster-based topology for 3D stacked architectures.	3DIC	2010	DBLP DOI BibTeX RDF
1	Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg	A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip.	DDECS	2010	DBLP DOI BibTeX RDF
1	Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila	Tree-model based mapping for energy-efficient and low-latency Network-on-Chip.	DDECS	2010	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip.	DDECS	2010	DBLP DOI BibTeX RDF
1	Kameswar Rao Vaddina, Tamoghna Mitra, Pasi Liljeberg, Juha Plosila	Thermal modelling of 3D multicore systems in a flip-chip package.	SoCC	2010	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Hossein Neishaburi, Siamak Mohammadi, Ali Afzali-Kusha, Juha Plosila, Hannu Tenhunen	An efficent dynamic multicast routing protocol for distributing traffic in NOCs.	DATE	2009	DBLP BibTeX RDF
1	Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila	Self-timed thermal sensing and monitoring of multicore systems.	DDECS	2009	DBLP DOI BibTeX RDF
1	Johanna Tuominen, Tomi Westerlund, Juha Plosila	Power Aware System Refinement.	Electr. Notes Theor. Comput. Sci.	2008	DBLP DOI BibTeX RDF
1	Tomi Metsälä, Tomi Westerlund, Seppo Virtanen, Juha Plosila	Rigorous Communication Modelling at Transaction Level With Systemc.	ICSOFT (SE/MUSE/GSDCA)	2008	DBLP BibTeX RDF
1	Tero Säntti, Joonas Tyystjärvi, Juha Plosila	A novel hardware acceleration scheme for java method calls.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Area efficient delay-insensitive and differential current sensing on-chip interconnect.	SoCC	2008	DBLP DOI BibTeX RDF
1	Teijo Lehtonen, Pasi Liljeberg, Juha Plosila	Online Reconfigurable Self-Timed Links for Fault Tolerant NoC.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, Jouni Isoaho	High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Tomi Westerlund, Juha Plosila	Time Aware System Refinement.	Electr. Notes Theor. Comput. Sci.	2007	DBLP DOI BibTeX RDF
1	Teijo Lehtonen, Pasi Liljeberg, Juha Plosila	Fault Tolerance Analysis of NoC Architectures.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Tomi Westerlund, Juha Plosila	Time Aware Modelling and Analysis of Multiclocked VLSI Systems.	ICFEM	2006	DBLP DOI BibTeX RDF	Timed Action Systems, formal methods, time, GALS
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Teijo Lehtonen, Pekka Rantala, P. Isomaki, Juha Plosila, Jouni Isoaho	An approach for analysing and improving fault tolerance in radio architectures.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere	Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications.	PDCAT	2006	DBLP DOI BibTeX RDF
1	Juha Plosila, Kaisa Sere, Marina A. Waldén	Asynchronous system synthesis.	Sci. Comput. Program.	2005	DBLP DOI BibTeX RDF
1	Tomi Westerlund, Juha Plosila	Formal Specification of a Protocol Processor.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Juha Plosila, Pasi Liljeberg, Jouni Isoaho	Modelling and Refinement of an On-Chip Communication Architecture.	ICFEM	2005	DBLP DOI BibTeX RDF
1	Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere	On-chip Debug for an Asynchronous Java Accelerator.	PDCAT	2005	DBLP DOI BibTeX RDF	Java, Debug, Embedded, Asynchronous, Co-design
1	Pasi Liljeberg, Juha Plosila, Jouni Isoaho	Self-timed communication platform for implementing high-performance systems-on-chip.	Integration	2004	DBLP DOI BibTeX RDF
1	Tiberiu Seceleanu, Juha Plosila	Constituent Elements of a Correctness-Preserving UML Design Approach.	IFM	2004	DBLP DOI BibTeX RDF	UML, refinement, Action Systems
1	Juha Plosila, Tiberiu Seceleanu, Pasi Liljeberg	Implementation of a Self-Timed Segmented Bus.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Juha Plosila, Tiberiu Seceleanu	Specification of an Asynchronous On-chip Bus.	ICFEM	2002	DBLP DOI BibTeX RDF
1	Juha Plosila, Kaisa Sere, Marina A. Waldén	Design with Asynchronously Communicating Components.	FMCO	2002	DBLP DOI BibTeX RDF
1	Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen	Interconnect peak current reduction for wavelet array processor using self-timed signaling.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Tiberiu Seceleanu, Juha Plosila	Formal Pipeline Design.	CHARME	2001	DBLP DOI BibTeX RDF
1	Pasi Liljeberg, Juha Plosila, Jouni Isoaho	Asynchronous interface for locally clocked modules in ULSI systems.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Juha Plosila, Tiberiu Seceleanu	Design of Synchronous Action Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Juha Plosila, Kaisa Sere	Action Systems in Pipelined Processor Design.	ASYNC	1997	DBLP DOI BibTeX RDF	pipelined processor design, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus, refinement calculus, action systems

Publications of "Juha Plosila" ( http://dblp.L3S.de/Authors/Juha_Plosila )