|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 16 occurrences of 16 keywords
|
|
|
|
|
Results
Found 30 publication records. Showing 30 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kai-hui Chang, Chris Browy |
Parallel Logic Simulation: Myth or Reality?  |
IEEE Computer  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov |
RTL analysis and modifications for improving at-speed test. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo |
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
Facilitating unreachable code diagnosis and debugging. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo |
Formal reset recovery slack calculation at the register transfer level. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo |
Applying verification intention for design customization via property mining under constrained testbenches. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko |
Logic synthesis and circuit customization using extensive external don't-cares. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
Optimizing blocks in an SoC using symbolic code-statement reachability analysis. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo |
Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco |
Incremental Verification with Error Detection, Diagnosis, and Visualization. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair |
|
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo |
Enhancing bug hunting using high-level symbolic simulation. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
bughunter, design for verification, symbolic simulation |
| 1 | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
RTL symbolic simulation, don't-care (DC), synthesis |
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
Customizing IP cores for system-on-chip designs using extensive external don't-cares. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors With Counterexamples and Resynthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Automating Postsilicon Debugging and Repair. |
IEEE Computer |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
SafeResynth: A new technique for physical synthesis. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Reap what you sow: spare cells for post-silicon metal fix. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Postplacement rewiring by exhaustive search for functional symmetries. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
VLSI, placement, rewiring |
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
Simulation-Based Bug Trace Minimization With BMC-Based Refinement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco |
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors with Counterexamples and Resynthesis. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking |
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Safe Delay Optimization for Physical Synthesis. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay |
| 1 | Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Node Mergers in the Presence of Don't Cares. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Automating post-silicon debugging and repair. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |
Automatic Partitioner for Behavior Level Distributed Logic Simulation. |
FORTE |
2005 |
DBLP DOI BibTeX RDF |
RTL level partitioner, behavior level partitioner, distributed simulation, parallel simulation |
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
Simulation-based bug trace minimization with BMC-based refinement. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |
A Temporal Assertion Extension to Verilog. |
ATVA |
2004 |
DBLP DOI BibTeX RDF |
temporal assertion, verification, PSL |
Displaying result #1 - #30 of 30 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")