Search results for "Karlheinz Meier"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Henry Markram, Karlheinz Meier, Thomas Lippert, Sten Grillner, Richard S. Frackowiak, Stanislas Dehaene, Alois Knoll, Haim Sompolinsky, Kris Verstreken, Javier DeFelipe, Seth Grant, Jean-Pierre Changeux, Alois Saria	Introducing the Human Brain Project.	Procedia CS	2011	DBLP DOI BibTeX RDF
1	Daniel Brüderle, Mihai A. Petrovici, Bernhard Vogginger, Matthias Ehrlich, Thomas Pfeil, Sebastian Millner, Andreas Grübl, Karsten Wendt, Eric Müller, Marc-Olivier Schwartz, Dan Husmann de Oliveira, Sebastian Jeltsch, Johannes Fieres, Moritz Schilling, Paul Müller, Oliver Breitwieser, Venelin Petkov, Lyle Muller, Andrew P. Davison, Pradeep Krishnamurthy, Jens Kremkow, Mikael Lundqvist, Eilif Mueller, Johannes Partzsch, Stefan Scholze, Lukas Zühl, Christian Mayr, Alain Destexhe, Markus Diesmann, Tobias C. Potjans, Anders Lansner, René Schüffny, Johannes Schemmel, Karlheinz Meier	A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.	Biological Cybernetics	2011	DBLP DOI BibTeX RDF
1	Daniel Brüderle, Johannes Bill, Bernhard Kaplan, Jens Kremkow, Karlheinz Meier, Eric Müller, Johannes Schemmel	Live demonstration: Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Daniel Brüderle, Johannes Bill, Bernhard Kaplan, Jens Kremkow, Karlheinz Meier, Eric Müller, Johannes Schemmel	Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Johannes Schemmel, Daniel Brüderle, Andreas Grübl, Matthias Hock, Karlheinz Meier, Sebastian Millner	A wafer-scale neuromorphic hardware system for large-scale neural modeling.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Sebastian Millner, Andreas Grübl, Karlheinz Meier, Johannes Schemmel, Marc-Olivier Schwartz	A VLSI Implementation of the Adaptive Exponential Integrate-and-Fire Neuron Model.	NIPS	2010	DBLP BibTeX RDF
1	Stefan Philipp, Johannes Schemmel, Karlheinz Meier	A QoS network architecture to interconnect large-scale VLSI neural networks.	IJCNN	2009	DBLP DOI BibTeX RDF
1	Bernhard Kaplan, Daniel Brüderle, Johannes Schemmel, Karlheinz Meier	High-conductance states on a neuromorphic hardware system.	IJCNN	2009	DBLP DOI BibTeX RDF
1	Johannes Fieres, Johannes Schemmel, Karlheinz Meier	Realizing biological spiking network models in a configurable wafer-scale hardware system.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Johannes Schemmel, Johannes Fieres, Karlheinz Meier	Wafer-scale integration of analog neural networks.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Eilif Mueller, Lars Buesing, Johannes Schemmel, Karlheinz Meier	Spike-Frequency Adapting Neural Ensembles: Beyond Mean Adaptation and Renewal Theories.	Neural Computation	2007	DBLP DOI BibTeX RDF
1	Johannes Schemmel, Daniel Brüderle, Karlheinz Meier, Boris Ostendorf	Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Daniel Brüderle, Andreas Grübl, Karlheinz Meier, Eilif Mueller, Johannes Schemmel	A Software Framework for Tuning the Dynamics of Neuromorphic Silicon Towards Biology.	IWANN	2007	DBLP DOI BibTeX RDF
1	Stefan Philipp, Andreas Grübl, Karlheinz Meier, Johannes Schemmel	Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections.	IWANN	2007	DBLP DOI BibTeX RDF
1	Martin Trefzer, Jörg Langeheine, Karlheinz Meier, Johannes Schemmel	A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.	AHS	2006	DBLP DOI BibTeX RDF
1	Johannes Fieres, Johannes Schemmel, Karlheinz Meier	Training convolutional networks of threshold neurons suited for low-power hardware implementation.	IJCNN	2006	DBLP DOI BibTeX RDF
1	Johannes Schemmel, Andreas Grübl, Karlheinz Meier, Eilif Mueller	Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model.	IJCNN	2006	DBLP DOI BibTeX RDF
1	Johannes Fieres, Karlheinz Meier, Johannes Schemmel	A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware.	ANNPR	2006	DBLP DOI BibTeX RDF
1	Martin Trefzer, Jörg Langeheine, Karlheinz Meier, Johannes Schemmel	Operational Amplifiers: An Example for Multi-objective Optimization on an Analog Evolvable Hardware Platform.	ICES	2005	DBLP DOI BibTeX RDF
1	Jörg Langeheine, Martin Trefzer, Daniel Brüderle, Karlheinz Meier, Johannes Schemmel	On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA.	GECCO	2004	DBLP DOI BibTeX RDF
1	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer	Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
1	Martin Trefzer, Jörg Langeheine, Johannes Schemmel, Karlheinz Meier	New Genetic Operators to Facilitate Understanding of Evolved Transistor Circuits.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
1	Felix Schürmann, Karlheinz Meier, Johannes Schemmel	Edge of Chaos Computation in Mixed-Mode VLSI - A Hard Liquid.	NIPS	2004	DBLP BibTeX RDF
1	Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Meier, Johannes Schemmel, Felix Schürmann	Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms.	ICES	2003	DBLP DOI BibTeX RDF
1	Steffen G. Hohmann, Johannes Schemmel, Felix Schürmann, Karlheinz Meier	Exploring The Parameter Space Of A Genetic Algorithm For Training An Analog Neural Network.	GECCO	2002	DBLP BibTeX RDF
1	Felix Schürmann, Steffen G. Hohmann, Johannes Schemmel, Karlheinz Meier	Towards an Artificial Neural Network Framework.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
1	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel	Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
1	Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel	Initial Studies of a New VLSI Field Programmable Transistor Array.	ICES	2001	DBLP DOI BibTeX RDF
1	Johannes Schemmel, Karlheinz Meier, Felix Schürmann	A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms.	ICES	2001	DBLP DOI BibTeX RDF
1	Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel	A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
1	Jörg Langeheine, Simon Fölling, Karlheinz Meier, Johannes Schemmel	Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array.	ICES	2000	DBLP DOI BibTeX RDF
1	Markus Loose, Karlheinz Meier, Johannes Schemmel	Entwicklung einer Kamera mit adaptiven Photorezeptoren in analoger CMOS-Technologie.	DAGM-Symposium	1996	DBLP BibTeX RDF

Publications of "Karlheinz Meier" ( http://dblp.L3S.de/Authors/Karlheinz_Meier )