| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kai Du, Peter J. Varman, Kartik Mohanram |
High performance reliable variable latency carry select addition.  |
DATE  |
2012 |
DBLP BibTeX RDF |
|
| 1 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli |
An Efficient Gate Library for Ambipolar CNTFET Logic. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Masoud Rostami, Kartik Mohanram |
Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Zukoski, Xuebei Yang, Kartik Mohanram |
Universal logic modules based on double-gate carbon nanotube transistors. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram |
Reliability-driven don't care assignment for logic synthesis. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Xuebei Yang, Kartik Mohanram |
Robust 6T Si tunneling transistor SRAM design. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuebei Yang, Kartik Mohanram |
Unequal-error-protection codes in SRAMs for mobile multimedia applications. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai Du, Peter J. Varman, Kartik Mohanram |
Static window addition: A new paradigm for the design of variable latency adders. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram |
Graphene tunneling FET and its applications in low-power circuit design. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
graphene nanoribbons, tunneling fets, low-power |
| 1 | Xuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, Kartik Mohanram |
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
graphene nanoribbons, schottky-barrier, models, carbon nanotubes |
| 1 | Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram |
Dominant critical gate identification for power and yield optimization in logic circuits. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
low-vt, process variations, yield |
| 1 | Masoud Rostami, Kartik Mohanram |
Novel dual-Vth independent-gate FinFET circuits. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken |
TIMBER: Time borrowing and error relaying for online timing error resilience. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken |
Analytical model for TDDB-based performance degradation in combinational logic. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli |
Power consumption of logic circuits in ambipolar carbon nanotube technology. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Kartik Mohanram |
Bi-decomposition of large Boolean functions using blocking edge graphs. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Giovanni De Micheli, Ioannis Xenarios |
Modeling stochasticity and robustness in gene regulatory networks. |
Bioinformatics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Kartik Mohanram |
Reliability Analysis of Logic Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Quming Zhou, Kartik Mohanram |
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. |
J. Electronic Testing |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Kartik Mohanram |
Timing-driven optimization using lookahead logic circuits. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
logic synthesis, timing optimization, lookahead |
| 1 | Mihir R. Choudhury, Kartik Mohanram |
Masking timing errors on speed-paths in logic circuits. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli |
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram |
Technology exploration for graphene nanoribbon FETs. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
graphene nanoribbons, variability, defects |
| 1 | Quming Zhou, Mihir R. Choudhury, Kartik Mohanram |
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. |
European Test Symposium |
2008 |
DBLP DOI BibTeX RDF |
filters, soft errors, circuit optimization, radiation hardening, fault avoidance |
| 1 | Mihir R. Choudhury, Kartik Mohanram |
Approximate logic circuits for low overhead, non-intrusive concurrent error detection. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram |
Error Detection and Tolerance for Scaled Electronic Technologies. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Jing Guo |
Graphene nanoribbon FETs: technology exploration and CAD. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mosin Mondal, Kartik Mohanram, Yehia Massoud |
Parameter-Variation-Aware Analysis for Noise Robustness. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Lin Zhong, Kartik Mohanram |
Power signal processing: a new perspective for power analysis and optimization. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
power simulation, power, signal processing, power analysis |
| 1 | Mihir R. Choudhury, Kartik Mohanram |
Accurate and scalable reliability analysis of logic circuits. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram |
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen |
Parallel domain decomposition for simulation of large-scale power grids. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Kartik Mohanram |
Gate sizing to radiation harden combinational logic. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alan L. Cox, Kartik Mohanram, Scott Rixner |
Dependable != unaffordable. |
ASID |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Kartik Mohanram |
Elmore model for energy estimation in RC trees. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
RC trees, interconnect, Energy estimation |
| 1 | Quming Zhou, Mihir R. Choudhury, Kartik Mohanram |
Design Optimization for Robustness to Single Event Upsets. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen |
Large power grid analysis using domain decomposition. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mihir R. Choudhury, Quming Zhou, Kartik Mohanram |
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram |
Simulation of transients caused by single-event upsets in combinational logic. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas |
Structure preserving reduction of frequency-dependent interconnect. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
interconnect, model-order reduction, skin effect |
| 1 | Kartik Mohanram |
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Nur A. Touba |
Lowering power consumption in concurrent checkers via input ordering. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Kartik Mohanram |
Analysis of delay caused by bridging faults in RLC interconnects. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Scott Rixner |
Context-Independent Codes for Off-Chip Interconnects. |
PACS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Quming Zhou, Kartik Mohanram |
Cost-effective radiation hardening technique for combinational logic. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Nur A. Touba |
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Nur A. Touba |
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Nur A. Touba |
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba |
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, C. V. Krishna, Nur A. Touba |
A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Mohanram, Nur A. Touba |
Input Ordering in Concurrent Checkers to Reduce Power Consumption. (PDF / PS) |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijit Jas, Kartik Mohanram, Nur A. Touba |
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing |
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