Search results for "Katarzyna Radecka"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic	Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Omid Sarbishei, Katarzyna Radecka	Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Zeljko Zilic, Katarzyna Radecka	Fault tolerant glucose sensor readout and recalibration.	Wireless Health	2011	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka, Zeljko Zilic	An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka	An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka	A novel method of synthesizing reversible logic.	ISCAS	2011	DBLP DOI BibTeX RDF
1	O. Sarbishei, Katarzyna Radecka	Analysis of Mean-Square-Error (MSE) for fixed-point FFT units.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Omid Sarbishei, Katarzyna Radecka	On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers.	IEEE Symposium on Computer Arithmetic	2011	DBLP DOI BibTeX RDF
1	Sayeeda Sultana, Katarzyna Radecka	Reversible implementation of square-root circuit.	ICECS	2011	DBLP DOI BibTeX RDF
1	Sayeeda Sultana, Katarzyna Radecka, Yu Pang	A study on relating redundancy removal in classical circuits to reversible mapping.	ICCD	2011	DBLP DOI BibTeX RDF
1	Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka	Positive Davio-based synthesis algorithm for reversible logic.	ICCD	2011	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka, Zeljko Zilic	Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	O. Sarbishei, Yu Pang, Katarzyna Radecka	Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks.	HLDVT	2010	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka, Zeljko Zilic	An efficient method to perform range analysis for DSP circuits.	ICECS	2010	DBLP DOI BibTeX RDF
1	O. Sarbishei, Katarzyna Radecka	Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka	Design for Testability of QCA Logic Under Stuck-at-value Fault Model.	Multiple-Valued Logic and Soft Computing	2008	DBLP BibTeX RDF
1	Yu Pang, Katarzyna Radecka	Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform.	DAC	2008	DBLP DOI BibTeX RDF	DSP circuit synthesis, optimization, error analysis, Taylor Series
1	Zeljko Zilic, Katarzyna Radecka	Scaling and Better Approximating Quantum Fourier Transform by Higher Radices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	quantum computing, Fourier transform, multivalued logic circuits, Walsh functions, multivariable systems
1	Ali Khazamipour, Katarzyna Radecka	Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology.	Multiple-Valued Logic and Soft Computing	2007	DBLP BibTeX RDF
1	Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur	Reversible circuit technology mapping from non-reversible specifications.	DATE	2007	DBLP DOI BibTeX RDF
1	Rong Zhang, Zeljko Zilic, Katarzyna Radecka	Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes.	VTS	2006	DBLP DOI BibTeX RDF
1	Katarzyna Radecka, Zeljko Zilic	Design Verification by Test Vectors and Arithmetic Transform Universal Test Set.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	arithmetic transform, Verification, spectral methods, error modeling, Universal Test Set, Reed-Muller transform, Walsh-Hadamard transform
1	Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka	Architectures of Increased Availability Wireless Sensor Network Nodes.	ITC	2004	DBLP DOI BibTeX RDF
1	Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka	FPGA Emulation of Quantum Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
1	Zeljko Zilic, Katarzyna Radecka	The Role of Super-Fast Transforms in Speeding Up Quantum Computations. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF
1	Katarzyna Radecka, Zeljko Zilic	Identifying Redundant Wire Replacements for Synthesis and Verification.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Katarzyna Radecka, Zeljko Zilic	Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Zeljko Zilic, Katarzyna Radecka	: Identifying redundant gate replacements in verification by error modeling.	ITC	2001	DBLP DOI BibTeX RDF
1	Katarzyna Radecka, Zeljko Zilic	Arithmetic Transforms for Verifying Compositions of Sequential Datapaths.	ICCD	2001	DBLP BibTeX RDF
1	Katarzyna Radecka, Zeljko Zilic	Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling.	VTS	2000	DBLP DOI BibTeX RDF	arithmetic transforms, functional verification, arithmetic circuits
1	Zeljko Zilic, Katarzyna Radecka	On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields.	ISSAC	1999	DBLP DOI BibTeX RDF
1	Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self-test for DSP cores.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF

Publications of "Katarzyna Radecka" ( http://dblp.L3S.de/Authors/Katarzyna_Radecka )