Search results for "Kaushik Roy"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Dongsoo Lee, Kaushik Roy	Viterbi-Based Efficient Test Data Compression.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	W. Paul Griffin, Anand Raghunathan, Kaushik Roy	CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Jaydeep P. Kulkarni, Kaushik Roy	Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Sang Phill Park, Dongsoo Lee, Kaushik Roy	Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy	Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems.	Signal Processing Systems	2012	DBLP DOI BibTeX RDF
1	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Georgios Panagopoulos, Charles Augustine, Kaushik Roy	A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach.	DATE	2012	DBLP BibTeX RDF
1	Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy	Layout-aware optimization of stt mrams.	DATE	2012	DBLP BibTeX RDF
1	Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy	Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Kaushik Roy	Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy	A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy	A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.	IEEE Trans. Circuits Syst. Video Techn.	2011	DBLP DOI BibTeX RDF
1	Soo Youn Kim, Selin Baytok, Kaushik Roy	Scaled LTPS TFTs for low-cost low-power applications.	ISQED	2011	DBLP DOI BibTeX RDF
1	Georgios Karakonstantis, Kaushik Roy	Voltage over-scaling: A cross-layer design perspective for energy efficient systems.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy	Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors.	ISLPED	2011	DBLP BibTeX RDF
1	Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy	IMPACT: imprecise adders for low-power approximate computing.	ISLPED	2011	DBLP BibTeX RDF
1	Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy	Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar	Dynamic effort scaling: managing the quality-efficiency tradeoff.	DAC	2011	DBLP DOI BibTeX RDF
1	Georgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy	Significance driven computation on next-generation unreliable platforms.	DAC	2011	DBLP DOI BibTeX RDF
1	Dongsoo Lee, Kaushik Roy	Viterbi-Based Efficient Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	On-Chip Decompressor, Scalability, Logic Test, Test Data Compression, Low-Power Test
1	Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy	Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy	Memory-based embedded digital ATE.	VTS	2011	DBLP DOI BibTeX RDF
1	Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy	Design of voltage-scalable meta-functions for approximate computing.	DATE	2011	DBLP BibTeX RDF
1	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Stage number optimization for switched capacitor power converters in micro-scale energy harvesting.	DATE	2011	DBLP DOI BibTeX RDF
1	Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan	MACACO: Modeling and analysis of circuits for approximate computing.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy	Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology.	ICCD	2011	DBLP DOI BibTeX RDF
1	Ik Joon Chang, Sang Phill Park, Kaushik Roy	Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy	Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy	Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy	On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy	Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Myeong-Eun Hwang, Kaushik Roy	ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jongsun Park, Jung Hwan Choi, Kaushik Roy	Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy	Self-Repairing SRAM Using On-Chip Detection and Compensation.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy	Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Patrick Ndai, Ashish Goel, Kaushik Roy	A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy	Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy	Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy	Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection.	ISLPED	2010	DBLP DOI BibTeX RDF	low power, epilepsy, biomedical, seizure detection
1	Georgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy	HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs.	ISLPED	2010	DBLP DOI BibTeX RDF	energy efficient systems, optimal design criteria, voltage-scaling
1	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Analysis and design of ultra low power thermoelectric energy harvesting systems.	ISLPED	2010	DBLP DOI BibTeX RDF	thermoelectric energy harvesting, ultra low power
1	Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy	Data-dependant sense-amplifier flip-flop for low power applications.	CICC	2010	DBLP DOI BibTeX RDF
1	Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar	Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.	DAC	2010	DBLP DOI BibTeX RDF	scalable effort, support vector machines, low power design, recognition, mining, approximate computing
1	Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy	Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras	Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Chao Lu, Vijay Raghunathan, Kaushik Roy	Micro-scale energy harvesting: a system design perspective.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy	Improved clock-gating control scheme for transparent pipeline.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Kaushik Roy, Byunghoo Jung, Anand Raghunathan	Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.	VLSI Design	2010	DBLP DOI BibTeX RDF	Heterogeneous integrated systems, More than Moore, Low-power, Hybrid systems
1	Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia	Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.	HOST	2010	DBLP DOI BibTeX RDF
1	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Efficient power conversion for ultra low voltage micro scale energy transducers.	DATE	2010	DBLP BibTeX RDF
1	Chao Lu, Vijay Raghunathan, Kaushik Roy	Maximum power point considerations in micro-scale solar energy harvesting systems.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Kaushik Roy, Alireza Alaei, Umapada Pal	Word-Wise Handwritten Persian and Roman Script Identification.	ICFHR	2010	DBLP DOI BibTeX RDF
1	Georgios Karakonstantis, Charles Augustine, Kaushik Roy	A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy	VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture.	ICCD	2010	DBLP DOI BibTeX RDF
1	Umapada Pal, Kaushik Roy, Fumitaka Kimura	A Lexicon-Driven Handwritten City-Name Recognition Scheme for Indian Postal Automation.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Jing Li, Kunhyuk Kang, Kaushik Roy	Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy	Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy	Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy	Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh	Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy	Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sang Phill Park, Kunhyuk Kang, Kaushik Roy	Reliability Implications of Bias-Temperature Instability in Digital ICs.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu	Impact of SoC power management techniques on verification and testing.	ISQED	2009	DBLP DOI BibTeX RDF
1	Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy	PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.	ISQED	2009	DBLP DOI BibTeX RDF
1	Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy	System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.	SiPS	2009	DBLP DOI BibTeX RDF
1	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.	ISLPED	2009	DBLP DOI BibTeX RDF	significance driven computation, variation aware, voltage over-scaling, low power, motion estimation
1	Kaushik Roy	Ultra low voltage CMOS.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive supply scaling, nano-scale cmos system, ultra low voltage design, ultra-dynamic voltage scaling
1	Umapada Pal, Rami Kumar Roy, Kaushik Roy, Fumitaka Kimura	Indian Multi-Script Full Pin-code String Recognition for Postal Automation.	ICDAR	2009	DBLP DOI BibTeX RDF
1	Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy	REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN.	CICC	2009	DBLP DOI BibTeX RDF
1	Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy	A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.	DAC	2009	DBLP DOI BibTeX RDF	low power SRAM, supply voltage over-scaling, graceful degradation
1	Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta	Device/circuit interactions at 22nm technology node.	DAC	2009	DBLP DOI BibTeX RDF	22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs
1	Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy	A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Mesut Meterelliyoz, Kaushik Roy	Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy	An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy	Coping with Variations through System-Level Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Kaushik Roy	Design in the nano-scale Era: Low-power, reliability, and error resiliency.	SoCC	2009	DBLP DOI BibTeX RDF
1	Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy	Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy	Profit Aware Circuit Design Under Process Variations Considering Speed Binning.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Jongsun Park, Kaushik Roy	A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Low power VLSI design, Low computational complexity, Discrete cosine transform
1	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
1	Swarup Bhunia, Kaushik Roy	Low power design under parameter variations.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy	Thermal analysis of 8-T SRAM for nano-scaled technologies.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy	O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.	DAC	2008	DBLP DOI BibTeX RDF	STT MRAM, yield
1	Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy	Process variation tolerant SRAM array for ultra low voltage applications.	DAC	2008	DBLP DOI BibTeX RDF	Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance
1	Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy	NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Kaushik Roy	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.	VTS	2008	DBLP DOI BibTeX RDF	Design, yield, failure, SRAM, variation
1	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Patrick Ndai, Kaushik Roy	A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.	DATE	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda	Soft Errors: System Effects, Protection Techniques and Case Studies.	DATE	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen	Power-Aware Testing and Test Strategies for Low Power Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Charles Augustine, Kaushik Roy	Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems.	DFT	2008	DBLP DOI BibTeX RDF
1	Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy	Tutorial: SoC Power Management Verification and Testing Issues.	MTV	2008	DBLP DOI BibTeX RDF
1	Kaushik Roy, Kinshuk Majumder	Trilingual Script Separation of Handwritten Postal Document.	ICVGIP	2008	DBLP DOI BibTeX RDF

Publications of "Kaushik Roy" ( http://dblp.L3S.de/Authors/Kaushik_Roy )