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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 31 publication records. Showing 31 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kentaroh Katoh, Kazuteru Namba, Hideo Ito |
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Construction of BILBO FF with Soft-Error-Tolerant Capability. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
Two-rail logic circuit, overtesting, testability, monotone function, path delay fault testing |
| 1 | Kazuteru Namba, Kengo Nakashima, Hideo Ito |
Single-Event-Upset Tolerant RS Flip-Flop with Small Area. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Kazuteru Namba, Takashi Ikeda, Hideo Ito |
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Chiba Scan Delay Fault Testing with Short Test Application Time. |
J. Electronic Testing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito |
Quantitative Evaluation of Integrity for Remote System Using the Internet. |
PRDC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaroh Katoh, Kazuteru Namba, Hideo Ito |
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaroh Katoh, Kazuteru Namba, Hideo Ito |
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kentaroh Katoh, Kazuteru Namba, Hideo Ito |
Design for Delay Fault Testability of 2-Rail Logic Circuits. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
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| 1 | Shuangyu Ruan, Kazuteru Namba, Hideo Ito |
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
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| 1 | Kazuteru Namba, Yoshikazu Matsui, Hideo Ito |
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. |
J. Electronic Testing |
2009 |
DBLP DOI BibTeX RDF |
IP core testing, Fixing-flipping coding, Fixing-shifting-flipping coding, Test compression, Reconfigurable network |
| 1 | Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito |
Dependability Evaluation for Internet-Based Remote Systems. |
PRDC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito |
A Delay Measurement Technique Using Signature Registers. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Takumi Hoshi, Kazuteru Namba, Hideo Ito |
Testing of Switch Blocks in Three-Dimensional FPGA. |
DFT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoichi Sasaki, Kazuteru Namba, Hideo Ito |
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch |
| 1 | Kazuteru Namba, Hideo Ito |
Path Delay Fault Test Set for Two-Rail Logic Circuits. |
PRDC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Delay Fault Testability on Two-Rail Logic Circuits. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuangyu Ruan, Kazuteru Namba, Hideo Ito |
Soft Error Hardened FF Capable of Detecting Wide Error Pulse. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Eiji Fujiwara |
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. |
Systems and Computers in Japan |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Takashi Ikeda, Kazuteru Namba, Hideo Ito |
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Redundant Design for Wallace Multiplier. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Proposal of Testable Multi-Context FPGA Architecture. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoichi Sasaki, Kazuteru Namba, Hideo Ito |
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Scan Design for Two-Pattern Test without Extra Latches. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Hideo Ito |
Design of Defect Tolerant Wallace Multiplier. |
PRDC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Eiji Fujiwara |
A class of systematic m-ary single-symbol error correcting codes. |
Systems and Computers in Japan |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuteru Namba, Eiji Fujiwara |
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. (PDF / PS) |
DFT |
2001 |
DBLP DOI BibTeX RDF |
error correcting-detecting code, unequal error protection code, burst error |
Displaying result #1 - #31 of 31 (100 per page; Change: )
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