Search results for "Kazutoshi Kobayashi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera	Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera	Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera	A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera	An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi	A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.	PRDC	2010	DBLP DOI BibTeX RDF
1	Michitarou Yabuuchi, Kazutoshi Kobayashi	Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations.	FPT	2010	DBLP DOI BibTeX RDF
1	Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Erect of regularity-enhanced layout on printability and circuit performance of standard cells.	ISQED	2009	DBLP DOI BibTeX RDF
1	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Hidetoshi Onodera	Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, routing, variation, yield enhancement
1	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera	A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LUT-based FPGA device, simple model circuit, ring oscillators, within-die variations, placement optimization, 90 nm
1	Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera	A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.	FPL	2006	DBLP DOI BibTeX RDF
1	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera	A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera	A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Hidetoshi Onodera	A Comprehensive Simulation and Test Environment for Prototype VLSI Verification.	IEICE Transactions	2004	DBLP BibTeX RDF
1	Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera	An SoC architecture and its design methodology using unifunctional heterogeneous processor array.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera	RTL/ISS co-modeling methodology for embedded processor using SystemC.	ISCAS	2004	DBLP BibTeX RDF
1	Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera	A vector-pipeline DSP for low-rate videophones.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Hidetoshi Onodera	ST: PERL package for simulation and test environment.	ISCAS	2001	DBLP DOI BibTeX RDF

Publications of "Kazutoshi Kobayashi" ( http://dblp.L3S.de/Authors/Kazutoshi_Kobayashi )