Search results for "Keishi Sakanushi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka	Electronic Triage System: Casualties Monitoring System in the Disaster Scene.	3PGCIC	2011	DBLP DOI BibTeX RDF
1	Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato	Biological information sensing technologies for medical, health care, and wellness applications.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Two-stage configurable decoder model for multiple forward error correction standards.	ESTImedia	2010	DBLP DOI BibTeX RDF
1	Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moneim Wahdan, Masaharu Imai	Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto	Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC	CoRR	2007	DBLP BibTeX RDF
1	Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
1	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa	Pack instruction generation for media pUsing multi-valued decision diagram.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-valued decision diagram, SIMD instructions
1	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Enabling RTOS simulation modeling in a system level design language.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC.	DATE	2005	DBLP DOI BibTeX RDF
1	H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Synthesizable HDL generation method for configurable VLIW processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Architecture-Level Performance Estimation for IP-Based Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
1	Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai	S-sequence: a new floorplan representation method preserving room abutment relationships.	ISCAS	2004	DBLP BibTeX RDF
1	Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai	A Code Selection Method for SIMD Processors with PACK Instructions.	SCOPES	2003	DBLP DOI BibTeX RDF
1	Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin	An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.	DATE	2002	DBLP DOI BibTeX RDF
1	Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita	The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.	ICCAD	1998	DBLP DOI BibTeX RDF
1	Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani	The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.	ICCAD	1998	DBLP DOI BibTeX RDF

Publications of "Keishi Sakanushi" ( http://dblp.L3S.de/Authors/Keishi_Sakanushi )