Search results for "Kenichi Okada"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa	Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Qinghong Bu, Ning Li, Kenichi Okada, Akira Matsuzawa	Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Kenichi Okada, You Nomiyama, Rui Murakami, Akira Matsuzawa	A Dual-Conduction Class-C VCO for a Low Supply Voltage.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa	A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Woogeun Rhee, Antonio Liscidini, Jae-Yoon Sim, Kenichi Okada, Sudhakar Pamarti	Clock/Frequency Generation Circuits and Systems.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa	A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa	A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ahmed Musa, Kenichi Okada, Akira Matsuzawa	A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Wei Deng, Kenichi Okada, Akira Matsuzawa	A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ning Li, Qinghong Bu, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa	Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa	Tunable CMOS Power Amplifiers for Reconfigurable Transceivers.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Rui Ito, Takahiro Sekiguchi, Mototsugu Hamada, Kenichi Okada	A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Ryo Minami, Jee Young Hong, Kenichi Okada, Akira Matsuzawa	Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yuya Ono, Takuichi Hirano, Kenichi Okada, Jiro Hirokawa, Makoto Ando	Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa	A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa	A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Yusaku Ito, Kenichi Okada, Kazuya Masu	A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers.	J. Electrical and Computer Engineering	2011	DBLP DOI BibTeX RDF
1	Wei Deng, Kenichi Okada, Akira Matsuzawa	A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa	A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa	A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Wei Deng, Kenichi Okada, Akira Matsuzawa	An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Shoichi Hara, Rui Murakami, Kenichi Okada, Akira Matsuzawa	The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Shoichi Hara, Kenichi Okada, Akira Matsuzawa	A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Keigo Bunsen, Kenichi Okada, Akira Matsuzawa	A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Ning Li, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa	Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Rui Murakami, Shoichi Hara, Kenichi Okada, Akira Matsuzawa	Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa	A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa	A 60GHz direct-conversion transmitter in 65nm CMOS technology.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Takahiro Fujishiro, Akane Sato, Yoko Kumagai, Tadashi Kaji, Kenichi Okada	Development of Hi-Speed X.509 Certification Path Validation System.	AINA Workshops	2010	DBLP DOI BibTeX RDF	Path Validation, Security, Certificate, PKI, X.509, Certification Path
1	Hirotaka Sugawara, Kenichi Okada, Kazuya Masu	Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Takeshi Ito, Kenichi Okada, Kazuya Masu	Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Akira Otsuki, Kenichi Okada	The study of the knowledge optimization tool.	GEC Summit	2009	DBLP DOI BibTeX RDF	new knowledge creation support, seci model, knowledge management
1	Akira Otsuki, Kenichi Okada	Construction of Optimized Knowledge and New Knowledge Creation Support Tool.	KES-AMSTA	2009	DBLP DOI BibTeX RDF	New knowledge creation support, SECI Model, Knowledge management
1	Kazuya Masu, Kenichi Okada	Reconfigurable RF CMOS Circuit for Cognitive Radio.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Win Chaivipas, Kenichi Okada, Akira Matsuzawa	Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Ning Li, Win Chaivipas, Kenichi Okada, Akira Matsuzawa	Analysis of CMOS Transconductance Amplifiers for Sampling Mixers.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Tackya Yammouch, Kenichi Okada, Kazuya Masu	Physical Modeling of MEMS Variable Inductor.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu	LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu	Small-area CMOS RF distributed mixer using multi-port inductors.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa	A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Shoichi Hara, Takeshi Ito, Kenichi Okada, Akira Matsuzawa	Design space exploration of low-phase-noise LC-VCO using multiple-divide technique.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu	Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.	ISQED	2007	DBLP DOI BibTeX RDF
1	Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu	Adaptable wire-length distribution with tunable occupation probability.	SLIP	2007	DBLP DOI BibTeX RDF	wire-length distribution, rent's rule
1	Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.	ASP-DAC	2007	DBLP DOI BibTeX RDF	intermodulation compensation, reconfigurable CMOS low noise amplifier, variable bias circuit, self compensation, power reduction
1	Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu	A Multi-Drop Transmission-Line Interconnect in Si LSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	K. Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu	A Wideband CMOS LC-VCO Using Variable Inductor.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wideband CMOS LC-VCO, variable inductor, tunable CMOS voltage controlled oscillator, switched capacitors, 1.28 to 2.75 GHz, CMOS process, 0.18 micron
1	Takumi Uezono, Kenichi Okada, Kazuya Masu	Statistical Modeling of a Via Distribution for Yield Estimation.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazuya Masu, Kenichi Okada, Hiroyuki Ito	RF Passive Components Using Metal Line on Si CMOS.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Takumi Uezono, Kenichi Okada, Kazuya Masu	Via Distribution Model for Yield Estimation.	ISQED	2006	DBLP DOI BibTeX RDF
1	Kenichi Okada, Takumi Uezono, Kazuya Masu	Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.	PATMOS	2006	DBLP DOI BibTeX RDF
1	D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu	Reconfigurable CMOS low noise amplifier for self compensation.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu	Wire Length Distribution Model for System LSI.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu	Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu	Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit.	IEICE Transactions	2005	DBLP BibTeX RDF
1	Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu	Evaluation of X Architecture Using Interconnect Length Distribution.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu	Wire Length Distribution Model Considering Core Utilization for System on Chip.	ISVLSI	2005	DBLP DOI BibTeX RDF	Wire Length Distribution, core utilization, layout-area allocation, SoC
1	Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu	Prediction of delay time for future LSI using on-chip transmission line interconnects.	SLIP	2005	DBLP DOI BibTeX RDF
1	Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu	A dynamic reconfigurable RF circuit architecture.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu	Evaluation of on-chip transmission line interconnect using wire length distribution.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu	Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design.	IEICE Electronic Express	2004	DBLP BibTeX RDF
1	Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu	ULSI Interconnect Length Distribution Model Considering Core Utilization.	DATE	2004	DBLP DOI BibTeX RDF

Publications of "Kenichi Okada" ( http://dblp.L3S.de/Authors/Kenichi_Okada )