Search results for "Keunwoo Kim"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yi-Bo Liao, Meng-Hsueh Chiang, Keunwoo Kim, Wei-Chou Hsu	Assessment of structure variation in silicon nanowire FETs and impact on SRAM.	Microelectronics Journal	2012	DBLP DOI BibTeX RDF
1	Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim	Technology-circuit co-design of asymmetric SRAM cells for read stability improvement.	CICC	2010	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj	FinFET SRAM Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	variability, SRAM, FinFET, Double gate
1	Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das	Yield estimation of SRAM circuits using "Virtual SRAM Fab".	ICCAD	2009	DBLP BibTeX RDF
1	Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka	Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang	Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.	ISQED	2008	DBLP DOI BibTeX RDF	PD/SOI, dopant fluctuation, sense amplifier, Variation
1	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
1	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.	Microelectronics Journal	2007	DBLP DOI BibTeX RDF
1	Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.	ISQED	2007	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang	Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	FD/SOI, low-power, stability, SRAM
1	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	Modeling and Analysis of Leakage Currents in Double-Gate Technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.	ISLPED	2005	DBLP DOI BibTeX RDF	double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
1	Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang	Nanoscale CMOS circuit leakage power reduction by double-gate device.	ISLPED	2004	DBLP DOI BibTeX RDF	double-gate device, short-channel effect, leakage power
1	Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim	Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
1	Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang	Strained-si devices and circuits for low-power applications.	ISLPED	2003	DBLP DOI BibTeX RDF	band offset, strained-Si MOSFET, mobility, SOI, SiGe

Publications of "Keunwoo Kim" ( http://dblp.L3S.de/Authors/Keunwoo_Kim )