| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Warin Sootkaneung, Kewal K. Saluja |
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate.  |
VLSI Design  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Ting Lin, Kewal K. Saluja, Seapahn Megerian |
Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors. |
Ad Hoc Networks |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Ya Huang, Parameswaran Ramanathan, Kewal K. Saluja |
Routing TCP Flows in Underwater Mesh Networks. |
IEEE Journal on Selected Areas in Communications |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan |
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita |
SEU tolerant SRAM cell. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja |
A low cost approach to calibrate on-chip thermal sensors. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Warin Sootkaneung, Kewal K. Saluja |
Soft error reduction through gate input dependent weighted sizing in combinational circuits. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Temperature Dependent Test Scheduling for Multi-core System-on-Chip. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
On Detecting Transition Faults in the Presence of Clock Delay Faults. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
Enhancement of Clock Delay Faults Testing. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
Clock line, Test Generation, Delay faults |
| 1 | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
Fault simulation and test generation for clock delay faults. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsuyoshi Iwagaki, Kewal K. Saluja |
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja |
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja |
Modeling latency - lifetime trade-off for target detection in mobile sensor networks. |
TOSN |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Warin Sootkaneung, Kewal K. Saluja |
On techniques for handling soft errors in digital circuits. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Yokoyama, Hideo Tamamoto, Kewal K. Saluja |
Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Ting Lin, Kewal K. Saluja, Parameswaran Ramanathan |
Connected Barrier Coverage on a Narrow Band: Analysis and Deployment. |
SECON |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Energy-efficient redundant execution for chip multiprocessors. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
redundant execution, microarchitecture, transient faults, permanent faults |
| 1 | Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita |
SEU tolerant SRAM for FPGA applications. |
FPT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. |
DSN |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi, Kewal K. Saluja |
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
post-silicon diagnosis, process variations |
| 1 | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
Modified T-Flip-Flop based scan cell for RAS. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
On Minimization of Test Application Time for RAS. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Random Access Scan (RAS), DFT, Scan Design |
| 1 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Ho-Yong Choi, Kewal K. Saluja |
Detection of inter-port bridging faults in dual-port memories. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
Test application time minimization for RAS using basis optimization of column decoder. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja |
Modeling Detection Latency with Collaborative Mobile Sensing Architecture. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyuchull Kim, Kewal K. Saluja |
Low-Area Wrapper Cell Design for Hierarchical SoC Testing. |
J. Electronic Testing |
2009 |
DBLP BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Power and thermal constrained test scheduling. |
ITC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Wang, Parmesh Ramanathan, Kewal K. Saluja |
Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions. |
SECON |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja |
DX-compactor: distributed X-compaction for SoCs. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
dx-compactor, hierarchical compactor, x-compactor, SoC, compaction |
| 1 | Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar |
False Path Aware Timing Yield Estimation under Variability. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar |
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Gh. Mohammad, Kewal K. Saluja |
Analysis and test procedures for NOR flash memory defects. |
Microelectronics Reliability |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing |
| 1 | Chao Wang, Parmesh Ramanathan, Kewal K. Saluja |
Calibrating Nonlinear Mobile Sensors. |
SECON |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja |
An accurate flip-flop selection technique for reducing logic SER. |
DSN |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan |
Implementing high availability memory with a duplication cache. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | X. Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja |
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. |
European Test Symposium |
2008 |
DBLP DOI BibTeX RDF |
At-Speed Scan Testing, Test Relaxation, X-Filling, Capture Mode, Yield Loss |
| 1 | Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja |
Moments Based Blind Calibration in Mobile Sensor Networks. |
ICC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Gh. Mohammad, Kewal K. Saluja |
Testing Flash Memories for Tunnel Oxide Defects. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang |
NBTI Degradation: A Problem or a Scare? |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara |
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita |
A Novel ATPG Method for Capture Power Reduction during Scan Testing. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara |
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiangning Yang, Kewal K. Saluja |
Combating NBTI Degradation via Gate Sizing. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja |
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja |
On NBTI Degradation Process in Digital Logic Circuits. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kim T. Le, Dong Hyun Baik, Kewal K. Saluja |
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu |
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti |
Energy Estimation of the Memory Subsystem in Multiprocessor Systems. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita |
A Per-Test Fault Diagnosis Method Based on the X-Fault Model. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara |
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
A New Method for Low-Capture-Power Test Generation for Scan Testing. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Lin Chin, Thomas Clouqueur, Parameswaran Ramanathan, Kewal K. Saluja |
Vulnerability of Surveillance Networks to Faults. |
IJDSN |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita |
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja |
Analytic modeling of detection latency in mobile sensor networks. |
IPSN |
2006 |
DBLP DOI BibTeX RDF |
collaborative detection, detection latency, analytic model, mobile sensor networks |
| 1 | Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja |
Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles. |
GLOBECOM |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Hyun Baik, Kewal K. Saluja |
Test Cost Reduction Using Partitioned Grid Random Access Scan. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja |
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja |
Efficient Test Set Modification for Capture Power Reduction. |
J. Low Power Electronics |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita |
On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Delay Fault Testing of Processor Cores in Functional Mode. |
IEICE Transactions |
2005 |
DBLP BibTeX RDF |
|
| 1 | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
Combinational automatic test pattern generation for acyclic sequential circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Gh. Mohammad, Kewal K. Saluja |
Optimizing program disturb fault tests using defect-based testing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu |
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita |
Fault Diagnosis of Physical Defects Using Unknown Behavior Model. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
Yield-Driven, False-Path-Aware Clock Skew Scheduling. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
performance-related circuit yield loss, circuit-level parameters, DFM, clock skew scheduling |
| 1 | Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja, Kuang-Ching Wang |
Exposure for collaborative detection using mobile sensor networks. |
MASS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
Low-capture-power test generation for scan-based at-speed testing. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara |
Design and analysis of multiple weight linear compactors of responses containing unknown values. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Hyun Baik, Kewal K. Saluja |
Progressive random access scan: a simultaneous solution to test power, test data volume and test time. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Testing Superscalar Processors in Functional Mode. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja |
A Class of Linear Space Compactors for Enhanced Diagnostic. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Hyun Baik, Kewal K. Saluja |
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
On Low-Capture-Power Test Generation for Scan Testing. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Marong Phadoongsidhi, Kewal K. Saluja |
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-based delay fault self-testing of pipelined processor cores. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Clouqueur, Kewal K. Saluja, Parameswaran Ramanathan |
Fault Tolerance in Collaborative Sensor Networks for Target Detection. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Collaborative target detection, value fusion, fault tolerance, sensor networks, decision fusion |
| 1 | Matthew L. King, Kewal K. Saluja |
Testing Micropipelined Asynchronous Circuits. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-Based Delay Fault Self-Testing of Processor Cores. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara |
Random Access Scan: A solution to test power, test data volume and test time. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Marong Phadoongsidhi, Kewal K. Saluja |
Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric F. Weglarz, Kewal K. Saluja, T. M. Mak |
Testing of Hard Faults in Simultaneous Multithreaded Processors. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
On per-test fault diagnosis using the X-fault model. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja |
Sensor Deployment Strategy for Detection of Targets Traversing a Region. |
MONET |
2003 |
DBLP DOI BibTeX RDF |
collaborative target detection, value fusion, sensor networks, deployment, exposure |
| 1 | Kewal K. Saluja |
Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. (PDF / PS) |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Gh. Mohammad, Kewal K. Saluja |
Stress Test for Disturb Faults in Non-Volatile Memories. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita |
Fault Diagnosis for Physical Defects of Unknown Behaviors. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
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